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How Do I Stimulate My Design?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn what a sequence in UVM is, how a sequence communicates with a driver, and how to start a sequence as part of your test. By the end of the lesson, you will understand how to define sequences that send transactions to the driver to create specific behaviors in your DUT, and how to initiate sequences from your test.
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How Do I Stimulate My Design?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn what a sequence in UVM is, how a sequence communicates with a driver, and how to start a sequence as part of your test. By the end of the lesson, you will understand how to define sequences that send transactions to the driver to create specific behaviors in your DUT, and how to initiate sequences from your test.
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How Do I Create Complex Test Scenarios?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn how a UVM virtual sequence coordinates the execution of other sequences and how to tailor your virtual sequence to your UVM environment. By the end of the lesson, you will understand how UVM virtual sequences allow you to define combinations of other sequences to create complex scenarios that generate traffic on multiple interfaces of your design, making it more likely to uncover unanticipated bugs.
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How Do I Create Complex Test Scenarios?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn how a UVM virtual sequence coordinates the execution of other sequences and how to tailor your virtual sequence to your UVM environment. By the end of the lesson, you will understand how UVM virtual sequences allow you to define combinations of other sequences to create complex scenarios that generate traffic on multiple interfaces of your design, making it more likely to uncover unanticipated bugs.
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osmosis 2024 – pushing the boundaries of formal verification
Resource (Verification Horizons Blog) - Dec 11, 2024 by Nicolae Tusinschi
The annual osmosis 2024 event has once again proved to be a powerful platform for advancing the field of verification. With a compelling agenda focused on integrating formal methods with simulation, automation, and emerging architectures, we gathered industry leaders and experts to explore cutting-edge solutions in verification.
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Boost Your Verification Productivity with Questa Verification IQ
Resource (Slides (.PDF)) - Nov 21, 2024 by Mark Carey
This session will explore Questa Verification IQ (VIQ), Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics, enhanced collaboration, and comprehensive traceability. By leveraging machine learning, VIQ significantly enhances verification efficiency to boost your productivity.
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Boost Your Verification Productivity with Questa Verification IQ
Webinar - Nov 21, 2024 by Mark Carey
In this webinar, you will learn how to implement a collaborative, plan-driven verification process, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results.
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Ensuring Robust Reset Integrity in Complex SoC Designs Through Advanced Reset Tree Checks
Resource (Verification Horizons Blog) - Nov 19, 2024 by Reetika - Siemens EDA
One of the foundational steps in the reset domain crossing (RDC) verification process is determining the structure of the reset tree within a system-on-chip (SoC) design. The reset tree is critical for tracking how reset signals propagate throughout the design, ensuring stable and predictable system operation. To construct this reset tree, engineers rely on static analysis techniques to examine the register transfer level (RTL) of the design and identify various reset signals.
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Effective Identification of Reset Tree Bugs to Mitigate RDC Issues
Resource (Paper (.PDF)) - Nov 15, 2024 by Reetika - Siemens EDA
This paper discusses these advanced structural checks, explaining how they are crucial for identifying potential issues early and ensuring the integrity of SoC designs.
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Effective Identification of Reset Tree Bugs to Mitigate RDC Issues
Paper - Nov 15, 2024 by Reetika - Siemens EDA
This paper emphasizes the importance of advanced reset tree structural checks to identify potential design issues prior to conducting RDC analysis. By doing so, these checks can significantly conserve both the time and effort expended by designers throughout the overall RDC verification process. This paper advocates for early detection and correction of such issues, underlining how advanced reset tree checks can enhance the integrity and reliability of SoC designs.
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Unlocking Performance: How Computational Storage Transforms Data Processing
Resource (Verification Horizons Blog) - Nov 07, 2024 by Ujjwal Negi
Computational storage devices (CSD) represent a paradigm shift in how data processing and storage are handled in modern data centers, providing significant benefits for applications requiring large-scale data management and real-time analytics.
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Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions
Resource (Slides (.PDF)) - Nov 06, 2024 by Rick Koster
This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.
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Capturing Additional DFT Coverage thru Functional Fault Grading
Resource (Slides (.PDF)) - Nov 06, 2024 by Byron Brinson
Today’s Semiconductors often target a manufacturing test coverage in excess of 99%. This target is particularly important for chips used in safety critical applications. However, there are usually a small number of faults that cannot be covered by structural testing. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.
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The New Leader in Verification IP: Questa + Avery Solution
Resource (Slides (.PDF)) - Nov 06, 2024 by Luis Rodriguez
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
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Questa Verification IQ: Boost verification predictability and efficiency with Big Data
Resource (Slides (.PDF)) - Nov 06, 2024 by Ahmed ElKady - Siemens EDA
VIQ is a collaborative, browser-based, data-driven platform that revolutionizes the verification process. By harnessing the power of machine learning, VIQ delivers advanced analytics, enhanced collaboration capabilities, and comprehensive traceability. This innovative approach significantly boosts verification efficiency, empowering you to maximize your productivity.
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Unlocking the Future of High Bandwidth Memory with Siemens and Rambus
Resource (Verification Horizons Blog) - Nov 05, 2024 by Dennis Brophy
HBM4 , the next-generation memory technology, is nearing finalization by JEDEC and promises to push the boundaries of data rate, 3D stack height, and DRAM chip density. This evolution from HBM3 to HBM4 means even higher bandwidth and greater device capacity, making it indispensable for the growing demands of AI and HPC applications.
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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications
Resource (Slides (.PDF)) - Oct 30, 2024 by Kamlesh Mulchandani
High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization.
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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications
Webinar - Oct 30, 2024 by Kamlesh Mulchandani
In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
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Analyze Architecture for Next Level Formal Unreachability Analysis
Resource (Slides (.PDF)) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische
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Analyze Architecture for Next Level Formal Unreachability Analysis
Resource (Recording) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische
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Automated Coverage Exclusions with Increase Coverage
Resource (Slides (.PDF)) - Oct 17, 2024 by Damian Savage - Arm
In these slides, you will be shown why considerable effort is required to meet 100% code coverage goals at Sub System (SS) level.
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Automated Coverage Exclusions with Increase Coverage
Resource (Recording) - Oct 17, 2024 by Damian Savage - Arm
In this video recording from osmosis 2024, Damian Savage from Arm, will guide as to why considerable effort is required to meet 100% code coverage goals at Sub System (SS) level.
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Designing Secure and Performant Out-of-Order Processors Enabled by Formal Verification
Resource (Recording) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University
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Designing Secure and Performant Out-of-Order Processors Enabled by Formal Verification
Resource (Slides (.PDF)) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University
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Comprehensive Flow for Ensuring Integrity and Security Through Formal Verification
Resource (Slides (.PDF)) - Oct 17, 2024 by Keerthi Devraj