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Context-Aware Debug for Complex Heterogeneous Environments

Webinar - May 21, 2020 by Rich Edelman

In this session, you will learn how you can debug using high level abstractions like classes, transactions, assertions, coverage, biometric search, automated temporal causality trace and how you can utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).
Productivity in the Questa Simulation Flow

Webinar - May 15, 2020 by Gordon Allan

In this session, you will learn every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.
Optimizing Time to Bug

Webinar - May 15, 2020 by Tom Fitzpatrick

In this session, we'll be highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must now be verified and managed and the safety and security of the data and systems they control.
UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know

Webinar - Apr 10, 2020 by Chris Spear

In this session, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.
Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

Webinar - Mar 31, 2020 by Chris Giles

This session will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
FPGA Verification Maturity: A Quantitative Analysis

Webinar - Mar 26, 2020 by Harry Foster

While multiple studies on IC/ASIC functional verification trends have been published, there have been no studies specifically focused on FPGA verification trends. To address this dearth of information, Harry presents the results from a recent large industry study on functional verification.
Why RDC Verification is an Emerging Requirement

Webinar - Oct 01, 2019 by Kurt Takara

In this session, you will learn what Reset-Domain Crossing (RDC) covers that Clock-Domain Crossing (CDC) does not and the appropriate time in the development cycle to deploy RDC.
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification

Webinar - Jul 10, 2019 by Kurt Takara

This session explains the importance of a complete Clock-Domain Crossing (CDC) methodology to produce error-free silicon.
Transaction Recording & Debug with Questa & Visualizer

Webinar - Jun 20, 2019 by Rich Edelman

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.
Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Webinar - Jun 20, 2019 by Ashish Amonkar

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
Low Power Verification Forum

Webinar - Feb 05, 2019 by Gordon Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Industry Advancements Required to Close the Power Management Verification Gap

Webinar - Jan 28, 2019 by Sriram Hariharan

In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
Deploying A Metrics Driven Low Power Methodology for Your RTL IP

Webinar - Jan 28, 2019 by Qazi Ahmed

In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
Low Power Verification & Analysis with Emulation

Webinar - Jan 28, 2019 by Shantanu Samant

In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
Productive Low Power Debug Across All Engines and Flows

Webinar - Jan 28, 2019 by Gordon Allan

In this session, we will answer the top nine questions asked for debugging low power in your design.
How to Unearth Deep Bugs Using Formal Bug Hunting Techniques

Webinar - Dec 23, 2018 by Mark Eslinger

In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.
UVM 1800.2 & The New and Improved UVM Cookbook

Webinar - Sep 11, 2018 by Tom Fitzpatrick

This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.
Using Automation to Close the Loop Between Functional Requirements and their Verification

Webinar - Aug 10, 2018 by Brian Craw

This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.
Requirement Tracing in the ISO 26262 World

Webinar - Mar 27, 2018 by Charles Battikha

In this session, you will learn about requirement tracing in ISO 26262 and the basics of the ISO 26262 standard as it applies to requirements for electronic design & verification of safety critical products.
Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs

Webinar - Mar 07, 2018 by Ellie Burns

In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

Webinar - Dec 12, 2017 by Neil Bulman

This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.
An Introduction to DO-254 and Advanced Verification

Webinar - Nov 02, 2017 by Tom Fitzpatrick

DO-254 describes the objectives of a verification process to allow the development of systems that meet your design assurance goals. This web seminar will explain the critical aspects of a DO-254-compliant process and show how many advanced verification techniques and tools may be applied to satisfy these objectives.
Coverage & Plan-Driven Verification for FPGAs

Webinar - Sep 06, 2017 by Brian Mathewson

This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.
SystemVerilog OOP Basics used in UVM Verification

Webinar - Jul 12, 2017 by Dave Rich

In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.
Breaking the Speed Limits on SoC Verification with Questa

Webinar - May 17, 2017 by Gordon Allan

In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.