Search Results
Filters
Advanced Search
210 Results
-
Industry Advancements Required to Close the Power Management Verification Gap
Webinar - Jan 28, 2019 by Sriram Hariharan
In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
-
Deploying A Metrics Driven Low Power Methodology for Your RTL IP
Webinar - Jan 28, 2019 by Qazi Ahmed
In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
-
Low Power Verification & Analysis with Emulation
Webinar - Jan 28, 2019 by Shantanu Samant
In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
-
Productive Low Power Debug Across All Engines and Flows
Webinar - Jan 28, 2019 by Gordon Allan
In this session, we will answer the top nine questions asked for debugging low power in your design.
-
How to Unearth Deep Bugs Using Formal Bug Hunting Techniques
Webinar - Dec 23, 2018 by Mark Eslinger
In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.
-
UVM 1800.2 & The New and Improved UVM Cookbook
Webinar - Sep 11, 2018 by Tom Fitzpatrick
This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.
-
Using Automation to Close the Loop Between Functional Requirements and their Verification
Webinar - Aug 10, 2018 by Brian Craw
This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.
-
How Formal Reduces Fault Analysis for ISO 26262
Webinar - Mar 27, 2018 by Doug Smith
In this session, you will learn how Formal reduces fault analysis for ISO 26262 with advanced techniques that eliminate large numbers of irrelevant faults without compromising the completeness of the verification, or the safety of the finished product.
-
Requirement Tracing in the ISO 26262 World
Webinar - Mar 27, 2018 by Charles Battikha
In this session, you will learn about requirement tracing in ISO 26262 and the basics of the ISO 26262 standard as it applies to requirements for electronic design & verification of safety critical products.
-
From Analysis to Fault Campaigns - ISO 26262
Webinar - Mar 27, 2018 by Charles Battikha
In this session, you will gain an understanding of the core mission, scope, and key concepts of ISO 26262 for automotive functional safety, analysis, and fault campaigns.
-
Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Webinar - Mar 07, 2018 by Ellie Burns
In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
-
Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
Webinar - Dec 12, 2017 by Neil Bulman
This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.
-
An Introduction to DO-254 and Advanced Verification
Webinar - Nov 02, 2017 by Tom Fitzpatrick
DO-254 describes the objectives of a verification process to allow the development of systems that meet your design assurance goals. This web seminar will explain the critical aspects of a DO-254-compliant process and show how many advanced verification techniques and tools may be applied to satisfy these objectives.
-
Coverage & Plan-Driven Verification for FPGAs
Webinar - Sep 06, 2017 by Brian Mathewson
This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.
-
SystemVerilog OOP Basics used in UVM Verification
Webinar - Jul 12, 2017 by Dave Rich
In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.
-
SoC Verification with the Questa Flow
Webinar - May 17, 2017 by Gordon Allan
In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.
-
Use Formal to Check Logic Faults
Webinar - Mar 17, 2017 by Mark Eslinger
In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.
-
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Webinar - Dec 05, 2016 by Kurt Takara
In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.
-
How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
Webinar - Dec 05, 2016 by Mark Eslinger
In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.
-
FPGA Prototyping: Maximize Your Enterprise Debug Productivity
Webinar - Nov 11, 2016 by Stephen Bailey
In this session, you will learn how to maximize your enterprise debug productivity.
-
Industry Trends in Today’s Functional Verification Landscape
Webinar - Nov 11, 2016 by Harry Foster
In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.
-
Enterprise Verification Debug and Analysis
Webinar - Nov 11, 2016 by Stephen Bailey
In this session, you will learn how debug and analysis fits into a platform-based verification solution.
-
System Level Debug & Analysis
Webinar - Nov 11, 2016 by Gordon Allan
In this session you will learn why block level methods don't work for system level verification and why design bugs commonly escape all the way to the prototyping lab and the debug technology alternatives available to address them.
-
Enterprise Debug for Formal
Webinar - Nov 11, 2016 by Joe Hupcey
In this session you learn more about formal-centric enterprise debug.
-
Enterprise Debug for Simulation
Webinar - Nov 11, 2016 by Moses Satyasekaran
In this session, you will learn more about common debug challenges and modern debug solutions.