FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

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BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

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Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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Webinar (225)
Intermediate (121)
Beginner (99)
Advanced (5)

225 Results

  • Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

    Webinar - Jul 22, 2026 by Kevin Urish

    In this session, we will equip you with comprehensive solutions to tackle current and emerging verification trends and compliance requirements for FPGA designs including optimizing verification productivity and quality and streamlining your high-level language verification flow for FPGA designs.

  • Resolve Metastability: Improve Your Clock Domain Crossing Verification with Questa CDC

    Webinar - Jun 10, 2026 by Ratko Raicki

    Do you have issues in fully verifying clocks in your design? Do you find CDC verification tasks daunting due to their complexities? Questa CDC offers a powerful, integrated approach to improve these verification processes. In this webinar, we will explain the major elements of CDC verification. With our differentiating features, we will highlight unique verification techniques in Questa, where verification of large numbers of CDC paths can be achieved easily.

  • Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

    Webinar - May 20, 2026 by Tufail Ansari

    In this webinar, we will talk about PCIe Gen8 Retimer and Optical retimer, and its key applications, which includes use of optical retimer in GPU and AI accelerators. Further, we will explain the Four-Retimer Aware (FRA) feature and the rules that apply to loopback, lane margining and SKP ordered sets.

  • Generating Quality Properties for Formal Verification of a Design

    Webinar - May 19, 2026 by Gerardo Nahum

    Improve productivity by generating properties using AI and enable on‑the‑spot syntactic and semantic verification. In this webinar, we will demonstrate how Questa One SFV provides critical prompts for AI agents and LLMs to produce usable properties. This session highlights seamless integration with VS Code, enabling property generation, property checking, and interactive property debugging within a familiar development environment.

  • From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

    Webinar - Apr 22, 2026 by Ronen Shoham

    In this webinar we will demonstrate how the Questa One Agentic Toolkit - announced in February 2026 and built on the industry-leading Questa One verification solution - transforms verification from isolated applications into intelligently orchestrated workflows through purpose-built Agentic AI that autonomously reasons, plans, and executes strategies while keeping engineers in the loop with approval controls at critical decision points.

  • Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

    Webinar - Mar 11, 2026 by Luis Rodriguez

    In this webinar we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.

  • Unlock Efficiency: Next-Gen Verification with Questa Check Register & Questa Check Connect

    Webinar - Feb 26, 2026 by Bobana Brzacki

    In this webinar you will learn about the automated verification of memory-mapped registers and connections in SOC designs. Questa Check Register and Questa Check Connect eliminate manual errors, accelerate verification processes, and ensure your registers and SOC connections are flawless and reliable. Perfect for teams looking to reduce time-to-market and improve design quality.

  • AI Assisted FPU Verification Using Questa One SFV

    Webinar - Feb 25, 2026 by Gerardo Nahum

    One of the key components of the AI revolution is Floating Point Hardware design. Design targeting AI requires at times fast computing with low precision and at times very high precision in its calculations. In this webinar we show how Questa One AI assisted tools for Static Formal, help to generate full formal verification checkers for user defined functionality including floating-point operations.

  • Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

    Webinar - Feb 18, 2026 by Jalaj Gupta

    This session highlights what’s new in PCIe Gen7 security and demonstrates how Avery Verification IP-built on deep PCIe and UCIe verification expertise-enables early validation of TDISP and IDE functionality, comprehensive protocol and security coverage, and faster compliance, reducing risk and time-to-market for secure PCIe designs.

  • Future-Proof Your Designs: The Power of Verify Property in Digital Verification

    Webinar - Feb 12, 2026 by Bobana Brzacki

    This webinar reveals cutting-edge tools that empower engineers to identify complex structural issues, connectivity errors, and X-propagation problems early in the design cycle without stimulus generation. Learn how to streamline your verification workflow, accelerate time-to-market, and deliver robust, high-quality designs while significantly reducing costly re-spins and debug cycles.

  • Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

    Webinar - Feb 11, 2026 by Kurt Takara

    This webinar will discuss how Questa CDC Power Aware analysis can address this problem, as well as describe how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.

  • Close Coverage Faster with Questa One Sim's Unreachability Analysis

    Webinar - Feb 05, 2026 by Justin Royse

    Coverage closure remains the single largest challenge facing functional verification teams today, affecting 34% of both ASIC and FPGA design projects. As verification approaches completion, coverage scores plateau well short of project goals—a phenomenon commonly known as the "Last Mile problem." This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.

  • Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X

    Webinar - Jan 29, 2026 by Bobana Brzacki

    In this webinar we introduce intuitive 'push-button' bug-hunting tools, Inspect and Check X, designed to transform your verification process. Join us for a practical deep dive into their core functionalities, demonstrating their efficient workflow from initial setup to insightful results analysis. You will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market.

  • Supercharge Your CDC & RDC Analysis with the Power of AI/ML

    Webinar - Jan 28, 2026 by Farhad Ahmed

    One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.

  • Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

    Webinar - Jan 21, 2026 by Sunil Sahoo

    This webinar will delve into  Questa One Sim’s groundbreaking metastability injection capability , a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic.

  • Formal Verification Made Simple: A Practical Guide for FPGA Designers

    Webinar - Jan 15, 2026 by Bobana Brzacki

    In this webinar we will demystify formal verification and show you how SFV fits naturally into your existing FPGA design flow. Whether you're working on control logic, interfaces, or complex state machines, you'll discover how formal can catch bugs that simulation misses - early, automatically, and exhaustively.

  • Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

    Webinar - Jan 14, 2026 by Abdelrahman Tharwat

    In this webinar, we’re excited to showcase the latest cutting-edge features of Questa One Sim, with UVVM (Universal VHDL Verification Methodology) . Learn how the newly added support for constrained randomization with multi-variable capabilities allows you to dynamically generate randomized, UVVM-compliant stimuli that address even the most intricate design constraints, helping you explore vast verification scenarios efficiently and effectively.

  • Debug Like a Pro: VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

    Webinar - Dec 03, 2025 by Mariam Maurice

    This webinar explores the debugging capabilities and best practices across the three leading VHDL verification (OSVVM, UVVM, UVM) frameworks.

  • Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

    Webinar - Nov 12, 2025 by Nicole Munson

    In this webinar, you will learn how Questa One Sim  empowers VHDL designers to dramatically enhance their debugging productivity. We'll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively, and streamline your entire VHDL RTL debug workflow.

  • HLV: Formal Verification of Synthesizable C++/SystemC Designs

    Webinar - Nov 05, 2025 by Vlada Kalinic

    Formal check tools are difficult to be analyzed on generated RTL (as the errors cannot be correlated to HLS source code) Catapult Formal/Onespin SystemC help to overcome this challenge. Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.

  • Improving Verification Productivity Using Questa One Sim

    Webinar - Oct 23, 2025 by Karim Ameziane

    This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. Furthermore, the webinar will showcase Questa One Sim's cutting-edge debugging tools. Experience how advanced capabilities like Protocol Debug, and X-Debug enhance productivity, enabling you to find bugs faster.

  • Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

    Webinar - Oct 15, 2025 by Justin Bunnell

    In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges. We will then explore the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.

  • Breaking Silos: Creating Synergistic Flows for Next-Gen Verification

    Webinar - Oct 08, 2025 by Kirolos Magdy

    In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows.

  • Did You Know QuestaSim Supports VHDL-2019?

    Webinar - Oct 01, 2025 by Abdelrahman Tharwat

    In this webinar, we will explore the VHDL-2019 supported features in QuestaSim such as; enhancing your VHDL testbench, accessing the host environment, assertion reporting, view modes for design configuration optimization and more.

  • Generating SystemVerilog Assertion (SVA) Properties with Property Assist

    Webinar - Jul 16, 2025 by Mark Eslinger

    In this webinar, you will learn how Questa Property Assist automatically generates SystemVerilog Assertions (SVA) that describe the behavior of hardware designs, using AI technology. In addition, Property Assist turns user prompts into optimized LLM prompts, retrieves LLM provided solutions, and presents the best generated SVA solutions for the user.