- Progyna Khondkar - Mentor, A Siemens Business
- Ping Yeung - Mentor, A Siemens Business
- Gabriel Chidolue - Mentor, A Siemens Business
Low power (LP) design verification is an emerging technology, and almost every chip design today incorporates UPF (IEEE-1801 standard) based power dissipation and reduction techniques to manage and control the power on chip. Coverage data from LP verification in general originates from UPF and relevant HDL objects, i.e. power domains, power supplies, power states, different power strategies, control signals and ports of the power strategies. Obviously the nature of power states and their transitions are quite different from non-LP state machines. In addition, the industry lacks in semantic references for formation of power state machines or power states and state-transition to develop a complete LP coverage computation models, as well an adaptable database with application programming interface (API) to collect, access and represent the computed LP coverage. In order to fulfill these missing pieces, we first identified all the resources of the LP coverage contributors and categorized them as UPF cover-bins. We also identified UPF cross-cover-bins for interdependent power states in a complex hierarchical UPF flow and proposed a simplified dependency graph to represent interdependent power states coverage computation models. Through real design examples and case studies, we demonstrate how to achieve comprehensive LP design verification closure with all possible sources of power states, their transition coverage and cross-coverage of power domains of interdependent states. As well the paper also proposes the mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with API accessibility.
Dynamic simulation results are inconclusive in nature and often need to be quantified with definitive metrics that possibly denote verification coverage closure through numeric values (in percentages) in conjunction with appropriate design parameters. Coverage provides meaningful insight into design verification completeness. The coverage metric in dynamic simulation is a system or standard of measurement used to describe the degree to which the design is exercised with certain design objects or parameters for a particular test suite or testplan execution. Even the testplan is subject to measurement as a weighted metric and recapitulated to contribute to the total resultant coverage metric for the design. The resultant metrics from such diversified objects or parameters are stored in a common, unified coverage database (UCDB). UCDB provides accessibility to further enhance the coverage metrics with new coverage results from different new sources through coverage merging, as well as a mechanism to analyze and generate the coverage reports through API, such as the industry standard Accellera UCIS API.
Unlike non-LP coverage, LP coverage data solely originates from the abstraction of UPF and relevant HDL objects. Moreover, in low power dynamic simulation state space, the UPF power states and their transitions are asynchronous in nature and may refer or depend on other power states. Even more than one power state can remain true at a time, while it is possible to mark any power state as illegal anytime. These unique but contradictory features of power states with respect to non-LP state machines make it difficult to formulate LP coverage computation models and coordinate with UCDB. Obviously the coverage information extraction from power states and their transitions are difficult and must rely on an exhaustive.
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Read the entire Low Power Coverage: The Missing Piece in Dynamic Simulation technical paper.
DVCon US 2018