Author:
- Saurabh Sharma - Mentor Graphics
Introduction:
No one can deny that you learn by experience, but it is often more prudent in the fast-paced world of high technology to learn from other people's experience.
In this spirit, the main aim of this paper is to make users aware of common pitfalls experienced while verifying PCI Express® (PCIe®) based NVM Express® (NVMe®) controllers. We will also demonstrate the effectiveness of the NVMe Questa Verification IP (QVIP) sequence library to verify these scenarios with ease and how NVMe QVIP can contribute in accelerating verification cycles.
NVMe is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe® based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and storage subsystems have a fundamentally different way to operate with host computers, unlike any previous storage protocol.
NVMe is an optimized, high-performance scalable host controller interface designed to address the needs of Enterprise and Client systems that utilize PCI Express-based solid-state storage. Designed to move beyond the dark ages of hard disk drive technology, NVMe is built from the ground up for non-volatile memory (NVM) technologies. NVMe is designed to provide efficient access to storage devices built with non-volatile memory — from today's NAND flash technology to future, higher performing, persistent memory technologies.
There are several performance vectors that NVMe addresses, including bandwidth, IOPs, and latency. For example, the maximum IOPs possible for Serial ATA was 200,000, whereas NVMe devices have already been demonstrated to exceed 1,000,000 IOPs. By supporting PCI Express and Fabrics such as RDMA and Fiber Channel, NVM Express can support much higher bandwidths than SATA or SAS (e.g., a PCI Express Gen3 x4 delivers 4 GB/s). Finally, next generation memory technologies may have read access latency under a microsecond, requiring a streamlined protocol that enables an end-to-end latency of under 10 microseconds, including the software stack. NVMe is a completely new architecture for storage, from the software stack to the hardware devices and systems.
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