- Rohit Jain - Mentor, A Siemens Business
- Shobana Sudhakar - Mentor, A Siemens Business
The exploding complexity of IC systems have contributed to the increase in challenges to verifying these designs. It is not uncommon to find designs that contain anywhere from a few million gates to hundreds of millions of gates, straining the limits of functional verification based on traditional simulation technologies. In response, verification processes are evolving with the wide adoption of sophisticated techniques, such as formal verification, that reduce
the amount of work required to achieve verification goals. However, despite being one of the oldest verifications flows, gate-level simulations (also known as, GLS) remain an integral part of product design sign-off. Since gate-level verification depends so heavily on simulation, any improvements to simulation methodology and technology can go a long way toward improving the overall verification efficiency.
In this paper, we will discuss the various methodologies and flows available for gate-level timing simulations and the scenarios that each flow is suitable for. This will help designer/validation engineers understand what these flows mean and make informed decisions when setting up a gate-level validation process; such as, what different timing modes (zero delay, unit delay, negative delay, etc.) should be used under what circumstances. This paper will also address the major pain points for gate-level validation engineers. These include efficiently improving debug of zero delay loops, X- tracing, and preventing zero-delay race conditions and feedback loops.
We will also touch upon methods to improve the validation of ATPG patterns and BIST tests. These tests often have a test set up phase, followed by multiple pattern test phases. We will discuss these different phases and how to best use them to create a methodology to improve the throughput of the serial and parallel ATPG pattern simulations. Throughput gains achieved in the multi-day pattern simulations can not only provide a significant boost to verification productivity, but also help realize faster turn-around times during debug cycles.
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Read the entire Efficient Modeling Styles and Methodology for Gate-Level Design Verification technical paper.