- Ahmed Yehia - Mentor Graphics
Registers and memory blocks are key parts of any design; a typical design could hold hundreds of them. Verifying the behavior of registers and memory blocks is an essential part in the verification process. There are many techniques for modeling and verifying hardware registers and memory blocks. In this paper, we focus on verifying hardware registers using register packages.
Verification and modeling of hardware registers and memory blocks via register packages is not a new trend. Many register packages from various vendors, written in different languages, currently exist and used in the industry. The Accellera VIP-TSC committee has made a significant progress in releasing the Universal Verification Methodology (UVM)  defining standards for creation, integration, and extension of verification environments. The UVM register library is an open source library, being part of the UVM library, which allows modeling and verification of hardware registers and memory blocks. Yet, the way the UVM register library is currently designed to layer registers and memories transactions on top of bus transactions, well suits low speed buses. On the other hand, it may not be efficient for high performance buses introducing undesired simulation performance degradation.
In the paper, we give a quick overview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks, showing the simulation performance bottlenecks observed when performing on high-speed buses. We then present an efficient overlay layer that can be easily integrated on top of the UVM register library, making the library suitable for high as well as low performance systems. Then we show how an efficient, yet powerful, registers to AMBA AXI bus transactions adapter would look like in this case. Finally, we provide a cost-benefit analysis on current and proposed implementations.
Naming some of the UVM register library features:
- Address management.
- Modeling registers and memory blocks.
- Front door and back-door access to Device under Verification (DUV).
- Implicit and explicit prediction of registers and memory blocks values.
- Coverage model API.
Usually the integration of a register library in a testbench environment requires four abstract steps: (1) building the register database, (2) writing registers and memory blocks test sequences, (3) configuring registers coverage as needed, and (4) integrating registers models and test sequences to the testbench verification components.
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Read the entire Boosting Simulation Performance of UVM Registers in High Performance Systems technical paper.