Verification Academy

Topic	Replies	Views	Activity
Difference between logic [7:0][3:0] ARRAY; and logic ARRAY [7:0][3:0]; in system verilog SystemVerilog	1	90	October 29, 2024
This is the code for finding maximum and minimum number in given array by using only constraint, but where I did mistake I am not getting? SystemVerilog SystemVerilog	1	103	August 30, 2024
# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq UVM uvm-ral	1	236	August 21, 2024
Query on uvm_reg_hw_reset_seq UVM RAL-UVM	1	101	August 19, 2024
Usage of DPI-C in C programming SystemVerilog SystemVerilog , DPI , C-programming-Verification-Hardware	1	280	June 18, 2024
Transfer transaction between sub-environment in uvmf UVM subenv	0	59	March 29, 2025
Best Way to Dynamically Index and Instantiate Submodules in SystemVerilog? SystemVerilog	3	49	February 18, 2025
Access internal reg and local param of the RTL from the sva file SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	2	33	May 21, 2025
Connect analysis_port to another analysis_port's provider UVM analysis_port	2	57	February 7, 2025
Can anyone check if assertion for 'ack goes high and stays high twice before the grant is issued. gnt must immediately follow ack.' correct or not? Or is there any easy approach? SystemVerilog	2	38	January 30, 2025
Legal declaration of concurrent assertion statement SystemVerilog SystemVerilog , assertion , SVA , concurrent-assertion	2	40	November 23, 2024
Assertion for credit based Design SystemVerilog	2	70	October 21, 2024
Using the string I provided in the create function UVM SystemVerilog , UVM	2	101	July 25, 2024
System verilog / UVM integer Overflow , Underflow SystemVerilog	2	263	July 16, 2024
SV Property - Using an absolute 1ns delay SystemVerilog	1	34	June 11, 2025
!UVM_ERROR! [NOTYPID] get_type not implemented in derived class. (:0) UVM	1	32	April 9, 2025
Implication operator in cover property Coverage	1	49	March 31, 2025
Incremental compilation or partition compilation SystemVerilog	1	38	March 24, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	45	March 23, 2025
Virtual Sequencer - Casting UVM	1	39	March 10, 2025
Response sequencer UVM	1	32	February 20, 2025
Doubt regarding non blocking assignment SystemVerilog	1	41	January 23, 2025
Accessing parent class variables in child class SystemVerilog	1	94	January 10, 2025
Disable keyword is not working when we launch threads with fork - join_none in a loop SystemVerilog fork-join	1	76	December 28, 2024
Variadic function and macro in SystemVerilog SystemVerilog SystemVerilog	1	109	December 27, 2024
C and SV handshake SystemVerilog SystemVerilog , C-programming-Verification-Hardware	1	137	October 10, 2024
Problem related to post increment and decrement SystemVerilog SystemVerilog	1	93	October 4, 2024
Overriding a component having imps by a component which redefines the imps UVM	1	96	August 28, 2024
How to check current repeat loop counter? SystemVerilog	1	119	August 8, 2024
Syntax error: token is '(' SystemVerilog SystemVerilog	1	225	June 23, 2024
UVMC 2.3.3 is compatible with uvm-ieee-2020 or not UVM UVMC-Compilation	0	48	November 25, 2024
How to coordinate TB with 2 Drivers UVM	0	133	August 16, 2024
Number of semaphore keys. created keys are not matching with get and put SystemVerilog SystemVerilog	4	35	May 28, 2025
How to compile common transaction class that is used in multiple agents UVM SystemVerilog	2	20	June 5, 2025
How to Ignore multiple bins in the function coverage using binsof & intersect? SystemVerilog	2	28	May 8, 2025
Getting the error of Got SIGSEGV An unexpected termination has occurred in /apps/vcsmx/vcs/U-2023.03-SP2/linux64/bin/vcs1 due to a signal: Segmentation fault Hostname b077b440f8e5 UVM UVM	2	315	June 24, 2024
How to specify coverbin for all negative integers Coverage Coverage	1	43	May 10, 2025
How to use SVA to check whether a multi-bit signal is going to change within 100 nanoseconds after the arrival of a signal rising edge? SystemVerilog	1	30	May 8, 2025
Defining specific bins SystemVerilog coverpoint	1	50	May 7, 2025
What is uvm_reg.has_reset(.delete(1))? UVM UVM	1	40	April 4, 2025
How to debug : never ending uvm_do UVM	1	41	March 19, 2025
UVM report catcher impact UVM UVM , report-catcher	1	34	March 11, 2025
How to pass a string of data when triggering a UVM event? UVM	1	45	March 6, 2025
Call python code from SV that consumes simulation time SystemVerilog	1	41	February 9, 2025
Generating two transactions SystemVerilog	1	32	February 7, 2025
Array Size is not getting allocated properly SystemVerilog SystemVerilog , randomization , Dynamic-Array	1	88	September 10, 2024
Input livelocks SystemVerilog assertion	1	117	September 9, 2024
Question about rand static property in class SystemVerilog	1	97	August 7, 2024
Continuous Assignment SystemVerilog	1	128	August 6, 2024
Declaration of a Default Value on 2 Dimensional Array SystemVerilog	1	197	July 23, 2024

Difference between logic [7:0][3:0] ARRAY; and logic ARRAY [7:0][3:0]; in system verilog

1

90

October 29, 2024

This is the code for finding maximum and minimum number in given array by using only constraint, but where I did mistake I am not getting?

SystemVerilog

1

103

August 30, 2024

# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq

UVM

uvm-ral

1

236

August 21, 2024

Query on uvm_reg_hw_reset_seq

UVM

RAL-UVM

1

101

August 19, 2024

Usage of DPI-C in C programming

SystemVerilog

SystemVerilog , DPI , C-programming-Verification-Hardware

1

280

June 18, 2024

Transfer transaction between sub-environment in uvmf

UVM

subenv

0

59

March 29, 2025

Best Way to Dynamically Index and Instantiate Submodules in SystemVerilog?

SystemVerilog

3

49

February 18, 2025

Access internal reg and local param of the RTL from the sva file

SystemVerilog

SystemVerilog , assertion , System-Verilog , SVA

2

33

May 21, 2025

Connect analysis_port to another analysis_port's provider

UVM

analysis_port

2

57

February 7, 2025

Can anyone check if assertion for 'ack goes high and stays high twice before the grant is issued. gnt must immediately follow ack.' correct or not? Or is there any easy approach?

SystemVerilog

2

38

January 30, 2025

Legal declaration of concurrent assertion statement

SystemVerilog

SystemVerilog , assertion , SVA , concurrent-assertion

2

40

November 23, 2024

Assertion for credit based Design

SystemVerilog

2

70

October 21, 2024

Using the string I provided in the create function

UVM

SystemVerilog , UVM

2

101

July 25, 2024

System verilog / UVM integer Overflow , Underflow

SystemVerilog

2

263

July 16, 2024

SV Property - Using an absolute 1ns delay

SystemVerilog

1

34

June 11, 2025

!UVM_ERROR! [NOTYPID] get_type not implemented in derived class. (:0)

UVM

1

32

April 9, 2025

Implication operator in cover property

Coverage

1

49

March 31, 2025

Incremental compilation or partition compilation

SystemVerilog

1

38

March 24, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure