Array Size is not getting allocated properly

SystemVerilog
, ,
1

Hai All,
Here is my sample code :

module tb;
  bit[15 : 0] cnt1;
  bit[15 : 0] cnt2;
  int cnt1xcnt2;
  //int cnt2;
  bit[7 : 0] data[];
  initial begin
    void'(std :: randomize(cnt2)with{cnt2 == 'd4;});
    void'(std :: randomize(cnt1)with{cnt1 == 'd54004;});
    $display("CNT1 %0d",cnt1);
    $display("CNT2 %0d",cnt2);
    cnt1xcnt2 = cnt1*cnt2;
    data = new[cnt1*cnt2];
    $display("array size before randomization : %0d",data.size());
    void'(std :: randomize(data) with {data.size() == cnt1*cnt2;});
    $display("array size after randomization : %0d",data.size());
  end
endmodule : tb

I am seeing this in the log

CNT1 54004
CNT2 4
array size before randomization : 19408
array size after randomization : 216016

There’s a mismatch in the expected size when i call the new method for the dynamic array initialization.
Can anyone provide some inputs here,
Here’s my EDA link : EDA Playground

2

If you try the other simulators, you will notice different results.

For the simulator you have specified, you are seeing the results of two 16 bit values being multiplied and being stored as a 16 bit value. To ensure correct results, you will want to cast the multiplication to an int so that there won’t be any overflow.