Call python code from SV that consumes simulation time

SystemVerilog
1

Hi, I have a python script which initializes register on a prototyping setup. I want to run this script in SV-UVM testbench to validate the script.

I’m able to call the py script in SV but for each py routine I want to call a driver task to execute the register initialization.

Suggestions???

2

“Consuming time” is a characteristic concept of hardware description languages. It requires a master scheduling kernel to keep all processes synchronized in time.

The SystemVerilog DPI lets you call a routine in another language and it can call back to another SystemVerilog routine which consumes time. At the moment, the only other language defined is C. But people have create wrapper interfaces for other languages like python. Here is one suggestion.

https://bitsbytesgates.com/python/2024/11/04/DPI_Isnt_Enough_MakingPythonPartOfYourSVTB.html