How to use SVA to check whether a multi-bit signal is going to change within 100 nanoseconds after the arrival of a signal rising edge?

such as PDOUT[15:0] and PRD

the period of clk = 1ns;

`timescale 1ns/1ps

assert property
(@(posedge clk)$rose(prd) |->  ##[0:100] $changed(pdout))

is it written correctly???