How to use SVA to check whether a multi-bit signal is going to change within 100 nanoseconds after the arrival of a signal rising edge?

SystemVerilog
1

such as PDOUT[15:0] and PRD

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image1443×540 102 KB

2

the period of clk = 1ns;

`timescale 1ns/1ps

assert property
(@(posedge clk)$rose(prd) |->  ##[0:100] $changed(pdout))

is it written correctly???