In C, we have the concept of variadic functions, which allow us to pass a varying number of arguments to a function. I am curious to know if SystemVerilog provides a similar capability, either for functions or macros.
SystemVerilog does not have this capability. Two other features lacking in SystemVerilog prevent this from being implemented.
Dynamic typing where a variable stores its type along with its value.
void pointer casting to different types
The nearest thing you can do is have a dynamic array of base objects as a function argument. Each argument would have to be a derivative of that base that you use use $cast to get to the actual argument.