C and SV handshake

SystemVerilog
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1

Hi,

Can someone explain the handshaking mechanism between the c and sv.
Where to start the test and where to end the test ?
How does the C or SV knows that the test has ended ?
When does the interrupt handling comes into the picture ?
When does the processor comes into the picture ?

Thanks

2

Your question needs a lot more specifics. C is a general programming language used for many purposes.

In hardware verification C can be used for generating stimulus, reference models, virtual prototyping, evaluation of results, and/or many other kinds of analysis.

And is your processor the Device Under Test (DUT), outside of the DUT, or IP included in the DUT.