Hi forum members
I had a small doubt. What if I have a situation where
assign c=a;
always_ff @(posedge clk)
Y<=c;
From the testbench if i drive a =1 at the posedge of the clk, will Y become 1 at that posedge in simulation?
Thank you
If a gets assigned in the active region, then c also gets assigned in the active region. You have a race condition between the two @(posedge clk) processes.
This is almost the same as the other question you asked a few months ago. Doubt regarding scheduling. See the links there