Doubt regarding scheduling

SystemVerilog
1

Hi forum members

I am new to verilog and I had a question. What if I have a situation where

assign c = a+b;

always_ff @(posedge clk) begin
if(c)
out<=1;
end

And a changes to 1 and b stays 0, at the rising edge of the clk. At that rising edge of clk, to evaluate out, will the new value of c ie 1 be used and make out 1?

Thank you.

2

It depends on what kind of assignment was made to a.

See Guidelines for using blocking and non blocking assignments in SV testbenches and Verilog 2001 styled testbenches when driving stimulus - #2 by dave_59

3

Thank you for your response Dave. So just to clarify, if a was made 1 with a non blocking assignment at posedge clk, then c would use the old value of a ie 0 because of which out would not update to 1?

4

Correct.