In reply to vk7715:
The general rule is if one process writes to a variable, and another process reads the same variable synchronized to the same event, avoid using blocking assignments to that variable in order to prevent race conditions. That applies to Verilog/SystemVerilog designs/testbenches.
The most common common mechanism is using non-blocking assignments. Other mechanisms are de-synchronizing the reading and writing processes with a delay or using a different clock edge.