Guidelines for using blocking and non blocking assignments in SV testbenches and Verilog 2001 styled testbenches when driving stimulus


As mentioned in the timeline, I am looking for guidelines as to when I must use non blocking and when to use blocking assignments.

From what I know, we must use non blocking while applying stimulus (driver), and blocking when sampling stimulus (monitor).

In a Verilog 2001 styled static testbench, I am guessing the same rule applies – use non blocking assignments when driving stimulus.

Can anyone confirm if these guidelines hold true in all cases? Are there any other guidelines for using blocking and non blocking when it comes to driving and sampling stimulus?


In reply to vk7715:

The general rule is if one process writes to a variable, and another process reads the same variable synchronized to the same event, avoid using blocking assignments to that variable in order to prevent race conditions. That applies to Verilog/SystemVerilog designs/testbenches.

The most common common mechanism is using non-blocking assignments. Other mechanisms are de-synchronizing the reading and writing processes with a delay or using a different clock edge.

In reply to dave_59:

Hi Dave, thank you for your response. If I want to sample data, am I allowed to use blocking assignments? I wanted to know if there are specific rules governing the sampling of data.

In reply to VE:

You need to avoid the case where:

  1. One process reads a variable
  2. another process writes to the same variable with a blocking assignment
  3. Both processes are synchronized to the same (clock) event.

In the case of the UVM monitor, the monitor calls a write() method of an analysis port, which calls the write() method in a scoreboard or analysis fifo. There is only one process.