Accessing parent class variables in child class

SystemVerilog
1

Hi,
In the following code, there are few variables in parent class which I need to access the value of it in the child class. I created a task disp(), which is called to update the main variables of parent class to a temporary variable.
Later in the child class, I am calling the super,disp() task to access the variable values in child class and this is printing as ‘0’. What is the issue in the code and what are the ways to access only the parent class variable values inside child class.

class A;
 int a;
 int b;
 int q[$];

 int a1;
 int b1;
 int temp_q1[$];

 task temp1;
   a = 10;
   b = 20;
   q.push_back(1); 
   q.push_back(2); 
   $display("A is %h, B is %h", a,b);
   $display("Queue size is %d", q.size());
   disp();
 endtask

 task disp();
   a1 = a;
   b1 = b;
   temp_q1 = q;
   $display("Inside Parent disp() %d.....%d....$d",a1,b1,temp_q1.size()); 
 endtask

endclass

class B extends A;
 int q1[$];
 int b_a1;

  task temp2;
    //super.temp1;
    $display("B:: A is %d, B is %d", super.a,super.b);
    $display("B:: Queue size is %d", super.q.size());
    super.disp();
  endtask

endclass

module temp1;
  A a_0;
  B b_0;

initial
begin
  a_0 = new();
  b_0 = new();
  a_0.temp1();
  b_0.temp2();
end

endmodule
2

You are using the terms ‘parent’ and ‘child’ which are incorrect in this scenario. In UVM, a ‘parent’ class will create an instance of a distinct ‘child’ class within it. There is no overlap between these two classes.

In your example, you are creating a ‘base’ class, and extending in to create an ‘extended’ class. The extended class will inherit all variables/methods of the base class, and also add additional variables/methods.

In your module temp1, you create two distinct instances, a_0 of class type A, and b_0 of class type B. Being two separate instances, you can’t access values from one instance in the other.

It is difficult to determine what you are expecting to see, but perhaps the following will demonstrate what you desire:

module temp1;
  A a_0;
  B b_0;

initial begin
  b_0 = new();
  a_0 = b_0;
  a_0.temp1();
  b_0.temp2();
end

endmodule