Verification Academy

Topic	Replies	Views	Activity
Converting string to HDL path SystemVerilog SystemVerilog	9	9554	September 29, 2018
Assertion Check SystemVerilog SystemVerilog , assertion , SVA	35	5010	May 11, 2021
Is fork join and fork join_any with wait fork perform the same operation? SystemVerilog SystemVerilog , System-Verilog , wait-fork	13	7964	December 26, 2019
Constraint to generate an array of random numbers where a certain value is repeated fixed number of times SystemVerilog SystemVerilog	18	6824	February 25, 2022
Passing parameters from command line UVM UVM , Command-Line-Processing , Parameters , valueplusargs	9	9283	February 19, 2020
Assertion using Generate Block Coverage Coverage , Assertions-using-Generate-Block	11	8376	March 30, 2015
Enum data type in embedded covergroup Coverage Coverage	10	8692	March 23, 2016
Constraint SystemVerilog SystemVerilog	22	5900	November 22, 2022
Foreach usage in randomization constraints SystemVerilog SystemVerilog , constraint-randomization , constraint-foreach-loop , constrained-random-generation , systemverilog-Arrays , constraint-dist	12	7683	November 7, 2021
Fork-join_none with delay SystemVerilog SystemVerilog , for-loop-fork-join_none	24	5487	February 15, 2023
Constraint for address to be inside 4k boundary SystemVerilog SystemVerilog , constraints	12	7585	September 3, 2021
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	7844	July 1, 2019
Assignment operation inside Assertion SystemVerilog SystemVerilog	17	6369	April 6, 2020
How to do conditional compilation according to macro's value? SystemVerilog SystemVerilog	10	8126	May 16, 2023
VHDL Record to SV structure SystemVerilog SystemVerilog	9	8458	November 11, 2019
[SVA] Pulse Width Assertion SystemVerilog SystemVerilog	10	7932	September 25, 2020
Why need dynamic array SystemVerilog SystemVerilog , why-need-dynamic-array-in-SV	9	8206	April 1, 2022
Any one please resolve this code Error In UVM Subscriber write function UVM UVM , UVM-Subscriber-write-method-error	12	7159	December 29, 2020
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	6355	April 7, 2024
Asynchronous reset assertion SystemVerilog SystemVerilog , assertion , reset	9	7972	December 28, 2018
How to compare the data between two uvm_tlm_analysis_fifo in scoreboard? UVM UVM , scoreboard , dual-port-ram	9	7721	July 19, 2017
RAL access stuck and not executed UVM UVM , RAL-stuck	27	4612	February 9, 2023
Query on Timescale directive limitation SystemVerilog SystemVerilog	11	7025	January 9, 2015
How to use simulator's command in OVM testcase OVM OVM	9	7671	January 21, 2016
Sum query on a Multi D array SystemVerilog SystemVerilog , constraint , constraint-arraysum	13	6428	October 10, 2019
Connection between driver and monitor UVM UVM	9	7569	December 20, 2016
SVA : Property is a tautology SystemVerilog SystemVerilog , SVA , Assertion-Based-Verification , SVA-Assertion , SVA-Arbiter	12	6471	March 30, 2021
SV bind in UVM where a parameter is used SystemVerilog SystemVerilog , UVM , parameter , SV-bind	10	6884	November 8, 2018
How to change severity of "UVM_ERROR: get: unable to locate hdl path" UVM UVM , uvm_error , locate-hdl-path	14	5873	September 30, 2016
A randomization question between a varible and a value UVM UVM	20	4779	May 6, 2015
2D array constraint randomization SystemVerilog SystemVerilog , 2D-array-SystemVerilog-randomization	17	5053	March 5, 2024
Backdoor acess through user defined maps UVM UVM , uvm_reg_map , DPI-backdoor-access	23	4325	September 2, 2019
Error regarding factory.print() UVM UVM , factoryprint	12	5866	September 15, 2016
Reversing a string SystemVerilog SystemVerilog	9	6663	December 30, 2015
Unwanted match of $fell at the first clock cycle SystemVerilog SystemVerilog	14	5393	June 7, 2023
How to write assertions for a Clock divider SystemVerilog SystemVerilog	13	5576	March 30, 2020
Constraint involving queues and arrays SystemVerilog SystemVerilog , constraints	9	6480	February 13, 2023
Image file read SystemVerilog SystemVerilog	9	6337	August 27, 2014
Pass variable from test to sequence UVM UVM	9	6306	February 22, 2024
Coding for covergroup with coverpoint and cross Coverage Coverage	13	5239	March 6, 2020
Scope of disable fork SystemVerilog SystemVerilog	15	4851	September 3, 2021
Do_copy method use? UVM UVM	11	5492	June 2, 2021
Nested Implication SystemVerilog SystemVerilog , assertion , nested-suffix-implication , sequences-and-properties	10	5675	June 13, 2023
Sequence access to a virtual interface UVM UVM	17	4387	August 5, 2016
Do we use modport of an interface when connecting to UVM test? UVM UVM , modport , Bus-interface , UVM-DUT-connection , SystemVerilog-modport , Interface-modport	10	5545	January 6, 2017
UVM_FATAL @ send_request failed to cast sequence item : error in sequence and sequencer SystemVerilog SystemVerilog , sequence-and-sequencer	10	5482	May 4, 2018
Assertion on req and gnt signals SystemVerilog SystemVerilog , SVA	14	4648	February 15, 2024
Randc variable not giving cyclic values UVM UVM	9	5640	August 22, 2018
How do get a report of which sequence is currently running on a sequencer? UVM UVM , uvm_sequence-uvm_sequencer	9	5532	November 16, 2016
Comparing Variable slices of Fixed Arrays SystemVerilog SystemVerilog , systemverilog-Arrays , compare	9	5509	May 22, 2023