Verilog-LRM defines that "The `timescale directive can result in file order dependency problems " .
Hence to recover this limitation System Verilog came up with timeunit and timeprecision declaration .
I was trying out with one example to justify the limitation of `timescale but I am not finding it working in Questasim10.0b .
I have pasted the codes below .
############# timescale.sv ##############
`timescale 10ns/1ps
module A;
reg a ;
initial
begin
a = 0;
#1;
a = 1;
end
endmodule
############# timescale_top.sv ############
`timescale 1ns/1ns
module timescale_top ;
reg b ;
initial
begin
b = 1;
#5;
b = 0;
end
A DUT_A();
endmodule
Observation : Variable “a” should read timescale directive of top module “timescale_top” instead it is reading its local module “timescale” timescale directive .
P.S : The `timescale directive only affects the current compilation unit; it does not span multiple compilation units .
Hence I have compiled the files by converting into single compilation unit as follows in-order to pick up the timescale of “timescale_top.sv” .
vlog -work work timescale.sv timescale_top.sv
It would be great if anyone can revert back with some ways to analyze the limitation .
Hierarchy does not affect how timescale directives are interpreted, only the compilation order of the source text. The #1 inside module A will always be interpreted as 1ns because of the timescale 1ns/1ps that appears at the beginning of the file. The scale of module timescale_top has no effect on module A regardless of using `timescale or timeunit.
Another issue is that the vlog command you show does not compile the files into a single compilation unit. By default, Questa treats each SystemVerilog file on the vlog command line as a separate compilation unit. For backward compatibility with Verilog *.v files are treated as a single compilation unit.
The file order dependency problem comes up when you compile multiple Verilog modules in files missing any `timescale directive. Suppose you had three files:
A.v
`timescale 10ns/1ps
module A;
reg a ;
initial
begin
a = 0;
#1;
a = 1;
end
endmodule
B.v
module B;
reg b ;
initial
begin
b = 0;
#2;
b = 1;
end
endmodule
C.v
`timescale 1ns/1ns
module top ;
reg c ;
initial
begin
c = 1;
#5;
c = 0;
end
A DUT_A();
B DUT_B();
endmodule
The #2 in module B could be interpreted as either 2ns or 20ns depending which file is compiled first. And if file B.v is compiled first, then you are relying on your tool to either set a default timescale, or give you an error stating that no timescale was specified.
SystemVerilog gives you a number of ways to handle this situation. The best thing to do is whenever you have a physical delay, specify the actual units by writing #2ns. Then there is no ambiguity in the scale of the delay. The other thing you can do is put a timeunit specification inside the body of the module instead of using the `timescale directive. The timeunit statement will have no effect on the modules that follow it.
Thank you for the explanation . Questasim throws error if any module doesn’t have timescale directive hence the problem is solved as it is mandatory to include timescale directive .
How about this below code?? Here the order of compilation doesn’t matter I feel so. It would be helpful if someone can correct me and tell more on this.
`timescale 1ns/1ns
module timescale_top ;
reg b;
reg c;
reg d;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
b = 1;
#5;
b = 0;
end
A DUT_A(.a(c));
B DUT_B(.p(d));
endmodule
`timescale 10ns/1ps
module A(a);
output a;
reg a;
initial begin
a=0;
#1;
a=1;
end
endmodule
`timescale 1ps/1ps
module B(p);
output p;
reg p;
initial begin
p=1;
#50;
p=0;
end
endmodule
$ vlog A.v B.v C.v
QuestaSim vlog 10.3 Compiler 2014.01 Jan 6 2014
Start time: 06:55:45 on Jan 07,2015
vlog A.v B.v C.v
-- Compiling module A
-- Compiling module B
-- Compiling module top
Top level modules:
top
End time: 06:55:45 on Jan 07,2015
Errors: 0, Warnings: 0
$ vsim -c top -do "run -all;quit"
Reading C:/questasim_10.3/tcl/vsim/pref.tcl
# 10.3
# vsim -do "run -all;quit" -c top
# Start time: 06:55:48 on Jan 07,2015
# ** Note: (vsim-8009) Loading existing optimized design _opt
#
# // Questa Sim
# // Version 10.3 win32 Jan 6 2014
# //
# // Copyright 1991-2014 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.top(fast)
# run -all
# quit
# End time: 06:55:48 on Jan 07,2015
# Errors: 0, Warnings: 0
SystemVerilog allows you to continuously assign one output port to a variable as long as there are no other continuous or procedural assignments to that variable. Verilog did not allow any continuous assignments to variables. See this. Most tools interpret files with *.sv filename extensions as SystemVerilog. Although not recommended, you can also add a global switch that interprets all files as SystemVerilog.
Abhyudha, the compilation order of the three files you show does not matter because you have placed a timescale directive in front of each module. The problem comes when you forget a timescale directive. In Verilog, you will not get any error unless you compile a module without a timescale directive first followed by modules with a timescale directive. Verilog treat all files as a single compilation unit, so the timescale in the first compiled file affects all subsequent files until encountering another timescale directive.
SystemVerilog addresses this issues in a number of ways by treating each file as separate compilation units and allowing you to introduce a timeunit statement inside a module so that the the timescale of one module has no effect on the timescale of subsequently compiled modules.
Dave I am using Questa10.0b
Please see below output :
##########################################################################
vsim -novopt work.timescale_top -c -do “run -all;exit”
Reading /home/maven/eda/modelsim/questa_sim/tcl/vsim/pref.tcl
You did not show the way you compiled the modules, but I assume you were compiling them as SystemVerilog files. In which case, each file is treated as a separate compilation unit.
HI Dave ,
Yes you are correct . I was compiling SV files.I made them verilog and could see that timescale directive spans across multiples files as they are treated as Single compilation unit in Verilog .