In reply to puttasatish:
How about this below code?? Here the order of compilation doesn’t matter I feel so. It would be helpful if someone can correct me and tell more on this.
`timescale 1ns/1ns
module timescale_top ;
reg b;
reg c;
reg d;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
b = 1;
#5;
b = 0;
end
A DUT_A(.a(c));
B DUT_B(.p(d));
endmodule
`timescale 10ns/1ps
module A(a);
output a;
reg a;
initial begin
a=0;
#1;
a=1;
end
endmodule
`timescale 1ps/1ps
module B(p);
output p;
reg p;
initial begin
p=1;
#50;
p=0;
end
endmodule