In reply to k@nth_nethula:
SystemVerilog allows you to continuously assign one output port to a variable as long as there are no other continuous or procedural assignments to that variable. Verilog did not allow any continuous assignments to variables. See this. Most tools interpret files with *.sv filename extensions as SystemVerilog. Although not recommended, you can also add a global switch that interprets all files as SystemVerilog.
Abhyudha, the compilation order of the three files you show does not matter because you have placed a timescale directive in front of each module. The problem comes when you forget a timescale directive. In Verilog, you will not get any error unless you compile a module without a timescale directive first followed by modules with a timescale directive. Verilog treat all files as a single compilation unit, so the timescale in the first compiled file affects all subsequent files until encountering another timescale directive.
SystemVerilog addresses this issues in a number of ways by treating each file as separate compilation units and allowing you to introduce a timeunit statement inside a module so that the the timescale of one module has no effect on the timescale of subsequently compiled modules.