Hierarchy does not affect how timescale directives are interpreted, only the compilation order of the source text. The #1 inside module A will always be interpreted as 1ns because of the timescale 1ns/1ps that appears at the beginning of the file. The scale of module timescale_top has no effect on module A regardless of using `timescale or timeunit.
Another issue is that the vlog command you show does not compile the files into a single compilation unit. By default, Questa treats each SystemVerilog file on the vlog command line as a separate compilation unit. For backward compatibility with Verilog *.v files are treated as a single compilation unit.
The file order dependency problem comes up when you compile multiple Verilog modules in files missing any `timescale directive. Suppose you had three files:
A.v
`timescale 10ns/1ps
module A;
reg a ;
initial
begin
a = 0;
#1;
a = 1;
end
endmodule
B.v
module B;
reg b ;
initial
begin
b = 0;
#2;
b = 1;
end
endmodule
C.v
`timescale 1ns/1ns
module top ;
reg c ;
initial
begin
c = 1;
#5;
c = 0;
end
A DUT_A();
B DUT_B();
endmodule
The #2 in module B could be interpreted as either 2ns or 20ns depending which file is compiled first. And if file B.v is compiled first, then you are relying on your tool to either set a default timescale, or give you an error stating that no timescale was specified.
SystemVerilog gives you a number of ways to handle this situation. The best thing to do is whenever you have a physical delay, specify the actual units by writing #2ns. Then there is no ambiguity in the scale of the delay. The other thing you can do is put a timeunit specification inside the body of the module instead of using the `timescale directive. The timeunit statement will have no effect on the modules that follow it.