Hi,
I have the put the hierarchies in hierarchy.txt file and when I am trying to read the same from my checker.sv(module) using fscanf, I am able to read the same as string.
But I want to convert the same string to hdl path and compare the same with default values which are coming from different default.txt file.
I am not able to convert the string to hdl path , and its trying to compare the string the bit.
Please assist me on this.
In reply to yaswanth021:
The SystemVerilog language, like most compiled languages, does not allow access to identifiers through string conversion. Interpreted languages like Tcl and Python let you compose code dynamically, so this is not an issue for them. However, you pay a big performance penalty for using an interpretive language.
Your most efficient option would be to somehow convert your two text files into SystemVerilog source code. It’s going to be difficult to show you how to do that without knowing the full extent of what you are trying to accomplish.
I’ll give you a few other suggestions, which involve turning off a number of optimizations to make sure the compiler does not optimize the signals away you want to access, and keeps the identifier names in database for you to look them up with a string.
You could write a VPI application in C. The VPI has routines to look up identifiers by string name and read their values. If you are good at writing C code, this might be the easiest thing to do.
Simulators provide tool specific routines to access signals by name from within your source code, or from an external simulation script. You’ll have to look in your tools manual for more information on that.
In reply to dave_59:
In reply to yaswanth021:
The SystemVerilog language, like most compiled languages, does not allow access to identifiers through string conversion. Interpreted languages like Tcl and Python let you compose code dynamically, so this is not an issue for them. However, you pay a big performance penalty for using an interpretive language.
Your most efficient option would be to somehow convert your two text files into SystemVerilog source code. It’s going to be difficult to show you how to do that without knowing the full extent of what you are trying to accomplish.
I’ll give you a few other suggestions, which involve turning off a number of optimizations to make sure the compiler does not optimize the signals away you want to access, and keeps the identifier names in database for you to look them up with a string.
You could write a VPI application in C. The VPI has routines to look up identifiers by string name and read their values. If you are good at writing C code, this might be the easiest thing to do.
Simulators provide tool specific routines to access signals by name from within your source code, or from an external simulation script. You’ll have to look in your tools manual for more information on that.
Hi Dave,
I was able to achieve the same using the UVM in-built function…
uvm_hdl_read , which takes string as input and gives values at the HDL path onto a variable.
In reply to yaswanth021:
Good. The UVM built-in functions use the VPI. You didn’t mention you were using the UVM.
In reply to dave_59:
This may be a reheated soup, but I am wondering:
what is the performance penalty when using uvm_hdl_read compared to a an access over the (known) hierarchy (e.g. assign local_sig = top.submodule.signal) ?
In reply to dipling:
The problem with accessing a signal using a string name is that the signal needs to be preserved; it cannot be optimized away. For example, it might be easier to evaluate the signal only when it gets used as part of another expression instead of trying to capture every possible intermediate value. The bigger problem is that the majority of users turn off all compiler optimizations with a global switch rather than going through the trouble of selecting just the required signal names.
In reply to dave_59:
Hi
How can i write multiple paths to single path in sv?
for example
i have
toop.rtl.p1
toop.rtl.p2
toop.rtl.p3
…
.
.
in this way there are many paths
i need to write in one single line
i cant write top.dut.p*
can you please me another way for this
Thanks
In reply to tejal vernekar:
If these paths really end in a numeric digit, get the RTL changed to use an array. We are 18 years into the 21st century after all.
Otherwise, the only other choices involve either tool-specific commands to find the signals you want to write to, or using the VPI.
In reply to dave_59:
These path do not end with numbers,but end with diff string
Like
toop.rtl.wnn
toop.rtl.wne
toop.rtl.wnb
Is there any any way ?
Thanks
In reply to tejal vernekar:
the only other choices involve either tool-specific commands to find the signals you want to write to, or using the VPI.