In reply to dave_59:
In reply to yaswanth021:
The SystemVerilog language, like most compiled languages, does not allow access to identifiers through string conversion. Interpreted languages like Tcl and Python let you compose code dynamically, so this is not an issue for them. However, you pay a big performance penalty for using an interpretive language.
Your most efficient option would be to somehow convert your two text files into SystemVerilog source code. It’s going to be difficult to show you how to do that without knowing the full extent of what you are trying to accomplish.
I’ll give you a few other suggestions, which involve turning off a number of optimizations to make sure the compiler does not optimize the signals away you want to access, and keeps the identifier names in database for you to look them up with a string.
You could write a VPI application in C. The VPI has routines to look up identifiers by string name and read their values. If you are good at writing C code, this might be the easiest thing to do.
Simulators provide tool specific routines to access signals by name from within your source code, or from an external simulation script. You’ll have to look in your tools manual for more information on that.
Hi Dave,
I was able to achieve the same using the UVM in-built function…
uvm_hdl_read , which takes string as input and gives values at the HDL path onto a variable.