In reply to dave_59:
This may be a reheated soup, but I am wondering:
what is the performance penalty when using uvm_hdl_read compared to a an access over the (known) hierarchy (e.g. assign local_sig = top.submodule.signal) ?
In reply to dave_59:
This may be a reheated soup, but I am wondering:
what is the performance penalty when using uvm_hdl_read compared to a an access over the (known) hierarchy (e.g. assign local_sig = top.submodule.signal) ?