How to do conditional compilation according to macro's value?

SystemVerilog
1

Hi,
In C, we can easily use the directive as,

if MACRO_A == VALUE_A

But in SV, for example, is there a way to achieve this using below code?

`define NUM_OF_INS 2

`if NUM_OF_INS == 2
....
`else
...
`endif

Thanks.

2

In reply to kooder:

There is no equivalent text macro in SystemVerilog.

The workaround depends on what code you are intending to put in each branch.

3

In reply to dave_59:
Thanks.

Then what would the workaround be like if I want to put some code in branch if, e.g,

`NUM_OF_INS == 2

Should I define another macro like

`define NUM_OF_INS_TWO

?

I prefer doing conditional compile only per the value of `NUM_OF_INS.

4

In reply to kooder:

If you had the code

if (`if (`NUM_OF_INS == 2) begin
    signal1 <= 5;
end else begin
    signal2 <=7;
end
 == 2) begin
    signal1 <= 5;
end else begin
    signal2 <=7;
end

That would work as long as NUM_OF_INS was always defined to be some integer expression. But like I said before, you need to show what you are trying to accomplish.

5

In reply to dave_59:

Yeah, my code looks like below,

`if `NUM_OF_INS == 2
assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
assert property (@(posedge clk) bb_seq |=> bb_exp[1] == bb_rtl[1]);
`else if `NUM_OF_INS == 1
assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
`endif

If NUM_OF_INS==2, two assertions are compiled, and if If NUM_OF_INS==1, only one assertion will be compiled. However, it seems SV only support directives like ifdef, but no if, so I have no idea on how to do conditional compile according to the value of the macro.

6

In reply to kooder:

There’s no need of a macro to do this. You can use an if, case, or for loop.

if (`NUM_OF_INS == 2) begin
  assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
  assert property (@(posedge clk) bb_seq |=> bb_exp[1] == bb_rtl[1]);
end else if (`NUM_OF_INS == 1) begin
  assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
end

See section 27 Generate constructs in the 1800-2017 LRM

7

In reply to dave_59:
Cool~ Thank you!

8

Hi,

I am facing similar problem. But a little difference is there. Based on macro value I have to compile different testcases
As follows

######################
ifdef VALUE equals 1 include “testcase_1.sv”
elsif VALUE equals 2 include “testcase_2.sv”
`endif

Thanks in advance

9

In reply to rithu_km:

If VALUE is being defined on the command line, it would be much easier to handle this in the compilation script or Makefile.

Otherwise you could do:

`define VALUE 1
`define QCONCAT(v1,v2) `"v1``v2.sv`"
`include `QCONCAT(testcase_,`VALUE)
10

In reply to dave_59:

Hi,
Fixed it in Makefile itself.
Thanks for the reply

11

In reply to dave_59:
Hi,

I’m trying to update a condition with MACRO value :

OpIsSequencer = (opcode == MATH) | (fmt = DF && (`RATE==SLOW));

In the above code RATE is a config parameter which can change to SLOW, FAST, MED

I’m facing compilation error for the same.
Kindly help fix this issue.