How to do conditional compilation according to macro's value?

SystemVerilog
6

In reply to kooder:

There’s no need of a macro to do this. You can use an if, case, or for loop.

if (`NUM_OF_INS == 2) begin
  assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
  assert property (@(posedge clk) bb_seq |=> bb_exp[1] == bb_rtl[1]);
end else if (`NUM_OF_INS == 1) begin
  assert property (@(posedge clk) bb_seq |=> bb_exp[0] == bb_rtl[0]);
end

See section 27 Generate constructs in the 1800-2017 LRM