How to do conditional compilation according to macro's value?

SystemVerilog
4

In reply to kooder:

If you had the code

if (`if (`NUM_OF_INS == 2) begin
    signal1 <= 5;
end else begin
    signal2 <=7;
end
 == 2) begin
    signal1 <= 5;
end else begin
    signal2 <=7;
end

That would work as long as NUM_OF_INS was always defined to be some integer expression. But like I said before, you need to show what you are trying to accomplish.