VHDL Record to SV structure

SystemVerilog
1

VHDL code:
type t_x is record
row: integer range 0 to 1023;
size: integer range 0 to 1023;
end record;

type x_array is array(7 downto 0) of t_x;

please provide
equivalent System Verilog code

2

In reply to Mallikarjun79:
You have two options:

  1. Use a struct definition. I like to include those in a package.
  2. Use a class definition, and instantiate that class with a new().
    The class offers much more flexibility, as you can extended it,
    and constraint randomize all objects of the class if they are
    pre-qualified with the rand
    Below is an example of those two techniques:

class R; 
	/* VHDL code:
       type t_x is record
       row: integer range 0 to 1023;
       size: integer range 0 to 1023;
       end record;
       type x_array is array(7 downto 0) of t_x; */
	bit[0:9] row, size; 	
	rand bit[0:9] rw, sz; 	
	endclass

package my_pkg;
	typedef struct {
		bit[0:9] row, size; 
	} t_x;
endpackage : my_pkg

module m; 
	import my_pkg::*; 
	t_x mrz; // from the package
	R r;
	bit clk, a;  
	bit[0:9] w, q;
	initial forever #10 clk=!clk;   
	initial begin  
		r=new(); 
		w=1023; q=70;
		r.row=w;
		r.size=q; 
		mrz.size=1023; 
		mrz.row=15;
 	  
		if (!randomize(r)  with 
		   { r.rw > 5; w <70; 
		     r.sz > 1; r.sz < 14;}) $error("randomization error"); 
	end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Both VHDL code and SV code will be in package.

VHDL code.

type t_x is record
row: integer range 0 to 1023;
size: integer range 0 to 1023;
end record;

type x_array is array(7 downto 0) of t_x;

SV code.
typedef struct {
int row, size;
} t_x;
My question is
How to declare the array of type t_x variable?
typedef t_x_array[0:7] t_x;
When tried this it is saying that t_x_array is unknown type.

please provide equivalent SV code for this (type x_array is array(7 downto 0) of t_x;)

4

In reply to Mallikarjun79:
The syntax is

typedef t_x x_array[7:0];

Note that some tools will allow you to share types in packages between VHDL and SystemVerilog so you only need to declare them in one package. Check your user manual.

5

Hi All,

In VHDL Record is there for combining two or more signals/ports and we can call the records in a single name of representation.

So in Verilog is there any equivalent keyword for the same.

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6

In reply to acemaria90:
In SystemVerilog, you can use the SystemVerilog interface to combine signals/ports. The interface is actually far more powerful than the VHDL record, as you can include functions, tasks, assertions, and computations with signal assignments and clocked procedures. The original Verilog does not support this capability; SystemVerilog is inclusive of Verilog.
Ben Cohen
http://www.systemverilog.us/

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
7

In reply to acemaria90:

The direct equivalent of a VHDL record is a SystemVerilog struct. An interface is certainly much more powerful as Ben states that gives you almost class-like functionality, but a struct may be more appropriate in many cases.

8

In reply to dave_59:

hello
I am trying to assign a signal from in-depth VHDL DUT hierarchy ot type

type mif_fifo_status_t is record
a : unsigned( 4 downto 0);
b : unsigned( 3 downto 0);
c : unsigned( 4 downto 0);
end record;

to a SV variable in the test bench of ttpue

typedef struct packed {

 logic unsigned [4:0] a;
 logic unsigned [3:0] b;
 logic unsigned [4:0] v;

} mif_fifo_status_t;

same type name, same field type and size
this.status = $root.tb.i_dut.carrier_a_block.i_a_h_hm2.i_hm_core.i_fifo_monitor.i_fifo1_i.mif_fifo_statu;
types are compiled in VHDL and verilog from two different files
I get

Time: 0 fs Iteration: 0 Region: /simutils_hm2_sv_unit File: …/tb/simutils_hm2.sv Line: 189

** Error: (vsim-13216) Illegal assignment to type ‘struct fifo_pkg::mif_fifo_status_t’ from type 'struct ': Struct/union types must match.

whatt’s wrong here?

thanks

9

In reply to stanzani:

SystemVerilog requires that structures have to be derived from the same type definition to be assignment compatible. It is not good enough to give two types the same name and same layout.

Please consult your tools User Manual as sharing types for mixed language simulations is a tool specific feature.

11

Hi Dave,

vhdl code

 type element; 
   type element_ptr is access element; 
   type element is 
      record 
         s1  : std_logic_vector(PAGE_ID_WIDTH-1 downto 0); 
         s2  : std_logic_vector(TAG_ID_WIDTH-1 downto 0);  
        age : time; 
        ptr1 : element_ptr; 
      end record;

Can you help me convert this vhdl into sv i am facing some error.
What i have done is…

SystemVerilog code

typedef struct element;
typedef element element_ptr;

   typedef struct {
    logic [PAGE_ID_WIDTH-1:0] s1;  
    logic [TAG_ID_WIDTH-1:0]  s2; 
    time age;
    element_ptr ptr1; 
  } element;
12

SystemVerilog does not have pointers to arbitrary variables. The most direct translation of this code would be to use a class

class element;
    logic [PAGE_ID_WIDTH-1:0] s1;  
    logic [TAG_ID_WIDTH-1:0]  s2; 
    time age;
    element ptr1; 
endclass

However, if the purpose of element is building a linked list, you could use a queue of structs instead of a class.