VHDL Record to SV structure

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Both VHDL code and SV code will be in package.

VHDL code.

type t_x is record
row: integer range 0 to 1023;
size: integer range 0 to 1023;
end record;

type x_array is array(7 downto 0) of t_x;

SV code.
typedef struct {
int row, size;
} t_x;
My question is
How to declare the array of type t_x variable?
typedef t_x_array[0:7] t_x;
When tried this it is saying that t_x_array is unknown type.

please provide equivalent SV code for this (type x_array is array(7 downto 0) of t_x;)