In reply to Mallikarjun79:
You have two options:
- Use a struct definition. I like to include those in a package.
- Use a class definition, and instantiate that class with a new().
The class offers much more flexibility, as you can extended it,
and constraint randomize all objects of the class if they are
pre-qualified with the rand
Below is an example of those two techniques:
class R;
/* VHDL code:
type t_x is record
row: integer range 0 to 1023;
size: integer range 0 to 1023;
end record;
type x_array is array(7 downto 0) of t_x; */
bit[0:9] row, size;
rand bit[0:9] rw, sz;
endclass
package my_pkg;
typedef struct {
bit[0:9] row, size;
} t_x;
endpackage : my_pkg
module m;
import my_pkg::*;
t_x mrz; // from the package
R r;
bit clk, a;
bit[0:9] w, q;
initial forever #10 clk=!clk;
initial begin
r=new();
w=1023; q=70;
r.row=w;
r.size=q;
mrz.size=1023;
mrz.row=15;
if (!randomize(r) with
{ r.rw > 5; w <70;
r.sz > 1; r.sz < 14;}) $error("randomization error");
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115