In reply to acemaria90:
In SystemVerilog, you can use the SystemVerilog interface to combine signals/ports. The interface is actually far more powerful than the VHDL record, as you can include functions, tasks, assertions, and computations with signal assignments and clocked procedures. The original Verilog does not support this capability; SystemVerilog is inclusive of Verilog.
Ben Cohen
http://www.systemverilog.us/
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448