UVM_FATAL @ send_request failed to cast sequence item : error in sequence and sequencer

SystemVerilog
,
1

Hi,

I was trying an example to start a sequence on sequencer. I am getting the below error:
UVM_FATAL @ 100: [simple_seqr ] ( 0) send_request failed to cast sequence item

Can someone help me with this please???

Below is my code:
----------------- sequence item -----------------
class simple_seq_item extends uvm_sequence_item;

rand real a;
rand real b;

function new(string name = “”);
super.new(name);
endfunction: new

uvm_object_utils_begin(simple_seq_item) uvm_field_real(a, UVM_ALL_ON)
uvm_field_real(b, UVM_ALL_ON) uvm_object_utils_end

endclass: simple_seq_item
----------------- sequencer ---------------------
class simple_sequencer extends uvm_sequencer#(simple_seq_item);

`uvm_component_utils(simple_sequencer)

//constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction

endclass
------------------- sequence ---------------------
class simple_sequence extends uvm_sequence#(simple_seq_item);

`uvm_object_utils(simple_sequence)

function new(string name = “simple_sequence”);
super.new(name);
endfunction: new

task body();

simple_seq_item req;

req = simple_seq_item::type_id::create("req");
start_item (req);
assert(req.randomize()) else `uvm_error("SIMPLE SEQ", "Randomization Failed");
req.print;
finish_item(req);

endtask: body

endclass: simple_sequence
---------------- driver --------------------------
class simple_driver extends uvm_driver#(simple_seq_item);
– some declarations
task run_phase(uvm_phase phase);
simple_seq_item req;
seq_item_port.get_next_item (req);
drive();
seq_item_port.item_done();
endtask
endclass
---------------- agent --------------------------
class simple_agent extends uvm_agent
simple_sequencer simple_seqr;
simple_driver simple_drvr;

task connect_phase(uvm_phase phase);
simple_drvr.seq_item_port.connect(simple_seqr.seq_item_export);
endtask
------------------ test -------------------------
class simple_test extends uvm_test
environment env;
simple_sequence simple_seq;

function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = environment ::type_id::create(.name(“env”), .parent(this));
simple_seq = simple_sequence ::type_id::create(.name(“simple_seq”) ,.parent(this));
endfunction

task run_phase(uvm_phase phase);
simple_seq.start(env.simple_ag.simple_seqr);
endtask

can someone please help me with this

2

In reply to manasa-n:

Two remarks:
(1) there is no need to create the simple_seq object during build_phase because it does not belong to the testbench hierarchy.
(2) Unfortunatly you do not show the environment clas.

Please format your code as SV!

3

In reply to chr_sue:

class environment extends uvm_env;
`uvm_component_utils(environment)

simple_agent simple_ag;

function void build_phase(uvm_phase phase);
super.build_phase(phase);
simple_ag = simple_agent::type_id::create(.name(“simple_ag”),.parent(this));
endfunction: build_phase

I tried removing the create of simple_seq object during build_phase but it gives me null object error.

Is there any thing wrong with the way i am calling the sequence.
I put displays in each step, but it looks like the driver is not coming out of get_seq_item.

4

In reply to manasa-n:

OK, the structural description does not look so bad.
Regarding the construction of the seq I meant it is not useful to do this in the build_phase.
But you have to create it in the run_phase.

Could you please implement the end_of_elaboration phase in the env and call there print_topology() like this

function void end_elaboration_phase (uvm_phase phase);
  super.end_elaboration_phase (phase);
  uvm_top.print_topology();
endfunction
5

In reply to chr_sue:

I got the below display:

UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:

Name Type Size Value

uvm_test_top base_test - @2894
env environment - @2976
simple_ag simple_agent - @3024
simple_drvr simple_driver - @4579
rsp_port uvm_analysis_port - @4678
seq_item_port uvm_seq_item_pull_port - @4629
simple_mntr simple_monitor - @4658
simple_seqr simple_sequencer - @3941
rsp_export uvm_analysis_export - @3998
seq_item_export uvm_seq_item_pull_imp - @4548
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1

6

In reply to manasa-n:

Does this reflect your testbench hierarchy?

Please modify the run_phase of your driver accordingly:

task run_phase(uvm_phase phase);
  simple_seq_item req;
  seq_item_port.get_next_item (req);
  `uvm_info(get_type_name(), req.sprint, UVM_MEDIUM) //diagnostic message
  drive();
  seq_item_port.item_done();
endtask

Please post some more data from your simulation log-file before the FATAL error.

7

In reply to chr_sue:
Hi,
Yes it reflects my testbench hierarchy.

i modified the run phase as above,

The display doesn’t come as the simulation gives a fatal error before the get_next_item is completed.
Please find the snip it of the log file:

UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘run’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘pre_reset’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘pre_reset’
UVM_INFO @ 0: [PH_READY_TO_END] (1227) Phase ‘uvm.uvm_sched.pre_reset’ (id=1482) PHASE READY TO END
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘reset’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘reset’
UVM_INFO @ 1: [SIMPLE DRIVER ] ( 24) INITIALIZE
UVM_INFO @ 1: [SIMPLE DRIVER ] ( 30) port connected to 1 export
UVM_FATAL @ 16: [simple_seqr ] ( 0) send_request failed to cast sequence item

8

In reply to manasa-n:

Then we have to debug the sequence processing.
Replace req.print with req.sprint and add the diagnostic message as shown below:

 task body();

   simple_seq_item req;
   req = simple_seq_item::type_id::create("req");
   start_item (req);
   `uvm_info(get_type_name(), "called start_item", UVM_MEDIUM)
   assert(req.randomize()) else `uvm_error("SIMPLE SEQ", "Randomization Failed");
   req.sprint;
   finish_item(req);
endfunction
9

In reply to chr_sue:

Hi,
I replaced my code with the above and i didn’t get the sprint display.

UVM_INFO @ 16: [simple_sequence] ( 17) called start_item
UVM_FATAL @ 16: [simple_seqr ] ( 0) send_request failed to cast sequence item

10

In reply to manasa-n:

This means you do not get an item when calling get_next_item.
I had a closer look to your code. Your sequence item has data members of data type real. They are not randomizable.
To exercise please replace the real by int and it should work.

11

In reply to chr_sue:

I changed the sequence item to int and it worked.

Thanks for the help!!!