UVM_FATAL @ send_request failed to cast sequence item : error in sequence and sequencer

SystemVerilog
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4

In reply to manasa-n:

OK, the structural description does not look so bad.
Regarding the construction of the seq I meant it is not useful to do this in the build_phase.
But you have to create it in the run_phase.

Could you please implement the end_of_elaboration phase in the env and call there print_topology() like this

function void end_elaboration_phase (uvm_phase phase);
  super.end_elaboration_phase (phase);
  uvm_top.print_topology();
endfunction