UVM_FATAL @ send_request failed to cast sequence item : error in sequence and sequencer

SystemVerilog
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2

In reply to manasa-n:

Two remarks:
(1) there is no need to create the simple_seq object during build_phase because it does not belong to the testbench hierarchy.
(2) Unfortunatly you do not show the environment clas.

Please format your code as SV!