In reply to chr_sue:
Hi,
Yes it reflects my testbench hierarchy.
i modified the run phase as above,
The display doesn’t come as the simulation gives a fatal error before the get_next_item is completed.
Please find the snip it of the log file:
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘run’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘pre_reset’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘pre_reset’
UVM_INFO @ 0: [PH_READY_TO_END] (1227) Phase ‘uvm.uvm_sched.pre_reset’ (id=1482) PHASE READY TO END
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘reset’
UVM_INFO @ 0: [PHASESEQ ] (1385) No default phase sequence for phase ‘reset’
UVM_INFO @ 1: [SIMPLE DRIVER ] ( 24) INITIALIZE
UVM_INFO @ 1: [SIMPLE DRIVER ] ( 30) port connected to 1 export
UVM_FATAL @ 16: [simple_seqr ] ( 0) send_request failed to cast sequence item