UVM_FATAL @ send_request failed to cast sequence item : error in sequence and sequencer

SystemVerilog
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6

In reply to manasa-n:

Does this reflect your testbench hierarchy?

Please modify the run_phase of your driver accordingly:

task run_phase(uvm_phase phase);
  simple_seq_item req;
  seq_item_port.get_next_item (req);
  `uvm_info(get_type_name(), req.sprint, UVM_MEDIUM) //diagnostic message
  drive();
  seq_item_port.item_done();
endtask

Please post some more data from your simulation log-file before the FATAL error.