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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

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      • Register Abstraction Layer
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    • Coding Guidelines & Deployment

      • Code Examples
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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    • Siemens EDA Learning Center

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      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Evolving Verification Capabilities

Evolving Verification Capabilities

Evolving Verification Capabilities Course | Subject Matter Expert - Harry Foster | Planning, Measurement and Analysis Topic

Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today's ASIC, FPGA and SoC design teams. Very few project managers would disagree with this statement. In fact, an often cited 2004 industry study by Collett International Research revealed that 35 percent of the total ASIC and FPGA development effort was spent in verification. In 2008, a Far West Research study (in conjunction with Mentor Graphics) indicated the verification effort has risen to 46 percent of the total ASIC and FPGA development effort.

Furthermore, these industry studies reveal that debugging is the fastest-growing component of verification, and that it consumes 60 percent of the total verification effort. Unfortunately, with the increase in verification effort, the industry has not experienced a measurable increase in quality of results. For example, a Collett International Research study that focused on design closure indicated that only 29 percent of projects developing ASICs and FPGAs were able to achieve first silicon success. To make matters worse, the industry is witnessing increasing pressure to shorten the overall ASIC, FPGA and SoC development cycle. Clearly, new design and verification techniques, combined with a focus on evolving an organization's functional verification process capabilities are required.

Functional verification flows that consist entirely of directed test and code coverage approaches (circa 1990 best practices) struggle to keep pace with today's verification challenges. In fact, there have been many helpful verification technologies that have emerged in the past 15 years (such as constrained-random, coverage-driven simulation; formal property checking; and assertion-based verification) that have demonstrated value by increasing productivity and achieving higher quality, as indicated both by those achieving first silicon success in the Collett and Far West studies.

This course provides a common framework for all advanced functional verification modules contained within the Verification Academy is recommended viewing. A simple Evolving Capabilities Model is presented, which can be used as a tool for assessing an organization's functional verification process capabilities.


Harry Foster
Planning, Measurement and Analysis
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Sessions

Introduction to the Verification Academy

Introduction to the Verification Academy Session | Subject Matter Expert - Harry Foster | Evolving Verification Capabilities Course

This session provides a common framework for all advanced functional verification modules contained within the Verification Academy.

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