New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

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Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

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SIEMENS Verification Academy

Progyna Khondkar

Progyna Khondkar, is a low power design & verification expert and senior verification engineer at Siemens EDA in the Design Verification Technology Division (DVT). He holds two patents and authored; [i]Low Power Design and Power Aware Verification[/i], that will be published from Springer in September 2017. He also has numerous publications in power aware verification. He has strong focus on electronics, computer and information science education, research and teaching experiences in top level universities in Asia. He has been working for hardware/software design, development, integration, test and verification in the world class ASIC & Electronic Design Automation (EDA) companies for last 15 years. He holds a Ph.D Computer Science and a senior member of IEEE. He also serves as a member of editorial board and reviewer of Journal of Information, IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, IEEE Transactions on Computers and Journal of VLSI Design and Verification (JVLSIDV).

Content by Progyna Khondkar

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