Prashant Dixit
Prashant Dixit has over 20 years of experience in the semiconductor industry, focusing on Verification IP development, IP/SoC Design and Verification.
Prashant is currently working as an Architect in developing Verification solutions for UCIe at Siemens EDA and is based out of Noida, India. He is also a member of the Verification IPs team that specializes in the development, testing and deployment of CXL, NVMe over PCIe and over Fabrics solutions.
Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed to the design and verification of IPs and SoC of networking and storage domains.
He completed his Master of Engineering in Microelectronics from BITS Pilani in 2006 and Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.
Content by Prashant Dixit
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From Manageability to 3.0: Unlocking the Future with UCIe Verification
Verification IP Sep 26, 2025 Ujjwal Negi link -
Verifying the Evolving UCIe Landscape: A 3.0-Aware Architecture for Manageability and Beyond
Verification IP Aug 13, 2025 Ujjwal Negi Paper -
Unlocking Performance: How Computational Storage Transforms Data Processing
Verification IP Nov 07, 2024 Ujjwal Negi link
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