New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

Register Now!

On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Available Now!

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Register Now!
SIEMENS Verification Academy

Avidan Efody

Avidan Efody is a verification architect for Siemens EDA, and an expert in listening to customers, distilling their problems, and helping them get to the optimal solution, preferably using Siemens EDA tools. Prior to moving to EDA Avidan has been architecting and coding testbenches in a variety of languages/methodologies for a variety of companies including PMC-Sierra, Infineon, TI, Nokia-Siemens and others. Recent problems he has been called to solve are fault analysis according to ISO 26262 specification, removal of adoption barriers for advanced verification methodologies within ISO 26262 and DO 254 flows, AMBA interconnect verification, Matlab-RTL integration and a few more. He’s proficient in SystemVerilog, OVM, UVM and a multitude of scripting languages such as Perl, TCL, PHP and JavaScript.

Content by Avidan Efody

Filters

Filter By

Subject Matter Experts