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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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June 2017 - Volume 13 Issue 2 (2)

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May 2020

Market-Driven Trends in Hardware Emulation
Acceleration May 21, 2020 Vijay Chobisa Webinar
Context-Aware Debug
Debug May 21, 2020 Rich Edelman Webinar
Productivity in the Questa Simulation Flow
FPGA Verification May 15, 2020 Gordon Allan Webinar
Optimizing Time to Bug
Planning, Measurement and Analysis May 15, 2020 Tom Fitzpatrick Webinar

April 2020

ISO 26262 Requirements Management
Functional Safety Apr 21, 2020 Jacob Wiltgen Session
ISO 26262 in Simple Terms
Functional Safety Apr 21, 2020 Jacob Wiltgen Session
ISO 26262 in Simple Terms
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
ISO 26262 Requirements Management
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
Introduction to ISO 26262
Functional Safety Apr 20, 2020 Jacob Wiltgen Track
UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know
SystemVerilog Apr 10, 2020 Chris Spear Webinar
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft pdf
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft Session

March 2020

Mind the GAP(s): Closing and Creating GAPS Between Design and Verification
Questa Design Solutions Mar 31, 2020 Chris Giles pdf
Mind the Gap(s): Closing and Creating Gaps Between Design and Verification
Questa Design Solutions Mar 31, 2020 Chris Giles Webinar
FPGA Verification Maturity: A Quantitative Analysis
FPGA Verification Mar 26, 2020 Harry Foster Webinar
FPGA Verification Maturity: A Quantitative Analysis
FPGA Verification Mar 26, 2020 pdf
Verify Thy Verifyer
UVM - Universal Verification Methodology Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - Verifworks Article
Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Formal Verification Mar 01, 2020 Tomáš Vaňák - Codasip Article
AI-Based Sequence Detection
Machine Learning Mar 01, 2020 Asif Ahmad, Abhishek Chauhan - Agnisys Article
An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Verification IP Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic Article
Formal Verification of RISC-V® Processors
Formal Verification Mar 01, 2020 Dr. Ashish Darbari Article

January 2020

Reset Verification in SoC Designs
Clock-Domain Crossing Jan 07, 2020 Kurt Takara Article
Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
Standards Jan 07, 2020 Matthew Ballance Article
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Standards Jan 07, 2020 Joe Hupcey Article

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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