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Show Less

March 2021

Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi Webinar
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Mark Eslinger Webinar
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara Webinar
Automatic Formal Verification - Questa Static and Formal Apps
Formal Verification Mar 21, 2021 Walter Gude Webinar
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Formal Verification Mar 18, 2021 Joon Hong Webinar
Practical Flows for Continuous Integration: Making the Most of Your EDA Tools
Questa Design Solutions Mar 16, 2021 Neil Johnson Webinar
Trends in Functional Verification
Planning, Measurement and Analysis Mar 02, 2021 Harry Foster Webinar

February 2021

I'm Excited About Formal...My Journey From Skeptic to Believer
Formal Verification Feb 26, 2021 Neil Johnson Webinar
A Methodology for Comprehensive CDC Analysis
Clock-Domain Crossing Feb 26, 2021 Atul Sharma Webinar
The ABC of Formal Verification
Formal Verification Feb 11, 2021 Dr. Ashish Darbari Webinar

July 2020

When Are You Done Running CDC?
Clock-Domain Crossing Jul 16, 2020 Chris Giles Webinar
Get Your Bits Together: SystemVerilog Structures and Packages
SystemVerilog Jul 14, 2020 Chris Spear Webinar
Simplifying Questa Usage and Deployment with Qrun
FPGA Verification Jul 09, 2020 Tom Kiley Webinar

June 2020

Introduction to Visualizer for VHDL Users
Debug Jun 30, 2020 Rich Edelman Webinar
Introduction to Visualizer for Verilog Users
Debug Jun 16, 2020 Rich Edelman Webinar
ISO 26262 Functional Safety for Autonomous Vehicles
Functional Safety Jun 11, 2020 Jake Wiltgen Webinar
Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
Clock-Domain Crossing Jun 11, 2020 Chris Giles Webinar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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