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November 2019

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UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf
UVM Connect 2.3.2 HTML
UVMC Nov 14, 2019 John Stickley tar
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf

October 2019

Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara pdf

September 2019

Questa SLEC Fact Sheet
Formal Verification Sep 30, 2019 Nicolae Tusinschi link
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf
Using HLS to Accelerate Computer Vision for Autonomous Drive
High-Level Synthesis Aug 20, 2019 pdf
Source Code Download: Fun with UVM Sequences - Coding and Debugging
Standards Aug 20, 2019 tar
Results Checking Strategies with Portable Stimulus
Portable Stimulus Aug 02, 2019 Tom Fitzpatrick pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman pdf

July 2019

Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick pdf
An Emulation Strategy for AI and ML Designs
Machine Learning Jul 15, 2019 Vijay Chobisa pdf
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf
Streamlining Plan & Requirements Driven Verification
Planning, Measurement and Analysis Jul 12, 2019 pdf
Improving Verification Throughput of Today’s Complex Mixed-Signal ICs
Analog Mixed-Signal Jul 12, 2019 pdf
Selecting the Most Productive SoC Design Verification Techniques
Planning, Measurement and Analysis Jul 12, 2019 pdf

FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

Browse all Resources in Siemens Verification Academy

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