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Show Less

April 2018

Basic Abstraction Techniques
Formal Verification Apr 14, 2018 pdf
Sequence Categories
UVM Framework Apr 12, 2018 Bob Oden pdf
Adding Tests and Sequences
UVM Framework Apr 12, 2018 Bob Oden pdf
Instantiating the DUT
UVM Framework Apr 12, 2018 Bob Oden pdf
Bench Code Generation
UVM Framework Apr 12, 2018 Jonathan Craft pdf
Probe Class
SystemVerilog Apr 01, 2018 Dave Rich link

March 2018

UVM Cookbook
UVM - Universal Verification Methodology Mar 15, 2018 Verification Methodology Team pdf
Questa VIP Integration
UVM Framework Mar 04, 2018 Dave Aerne pdf

February 2018

Testbench: Architecture and Operation
UVM Framework Feb 26, 2018 Bob Oden pdf
Environment Code Generation
UVM Framework Feb 26, 2018 Jonathan Craft pdf
Scoreboards and Predictors
UVM Framework Feb 26, 2018 Bob Oden pdf
Environments: Architecture and Operation
UVM Framework Feb 26, 2018 Bob Oden pdf
Interface Code Generation
UVM Framework Feb 26, 2018 Jonathan Craft pdf
Agents: Architecture and Operation
UVM Framework Feb 26, 2018 Bob Oden pdf
Code Generation Introduction
UVM Framework Feb 26, 2018 Jonathan Craft pdf
UVMF - Overview
UVM Framework Feb 26, 2018 Bob Oden pdf
UVMF - Series Introduction
UVM Framework Feb 26, 2018 Bob Oden pdf

November 2017

UVM Connect 2.3.1 Primer
UVMC Nov 08, 2017 John Stickley pdf
UVM Connect 2.3.1 Primer
UVMC Nov 08, 2017 John Stickley tar
UVM Connect 2.3.1 Kit
UVMC Nov 07, 2017 John Stickley tar

October 2017

DO-254 for FPGAs
Functional Safety Oct 17, 2017 Alex Grove - Siemens Eda pdf
Coverage & Plan Driven Verification for FPGAs Session
Verification Management Oct 17, 2017 pdf
Regression Management and Dev Ops
Verification Management Oct 17, 2017 pdf
FPGA Verification Introduction
FPGA Verification Oct 17, 2017 pdf
Testbench Acceleration
Acceleration Oct 17, 2017 pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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