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December 2020

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Dec 22, 2020 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 16, 2020 Harry Foster link
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Dec 09, 2020 Harry Foster link
Part 4: FPGA Verification Effort Trends (Continued)
Planning, Measurement and Analysis Dec 02, 2020 Harry Foster link

November 2020

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Nov 18, 2020 Harry Foster link
Part 2: FPGA Verification Effectiveness Trends
Planning, Measurement and Analysis Nov 10, 2020 Harry Foster link
I’m Excited About Formal…My Journey From Skeptic to Believer
Formal Verification Nov 09, 2020 pdf
Part 1: FPGA Design Trends
Planning, Measurement and Analysis Nov 05, 2020 Harry Foster link

October 2020

Understanding and Minimizing Study Bias (2020 Study)
Planning, Measurement and Analysis Oct 30, 2020 Harry Foster link
ISO 26262 Fault Campaign Management
Functional Safety Oct 29, 2020 Jacob Wiltgen pdf
Prologue: The 2020 Wilson Research Group Functional Verification Study
Planning, Measurement and Analysis Oct 27, 2020 Harry Foster link
FPGA Functional Verification Trend Report - 2020
FPGA Verification Oct 13, 2020 Harry Foster pdf
IC/ASIC Functional Verification Trend Report - 2020
Planning, Measurement and Analysis Oct 13, 2020 Harry Foster pdf

September 2020

ISO 26262 Bottoms-Up Safety Analysis
Functional Safety Sep 29, 2020 Jacob Wiltgen pdf

July 2020

When Are You Done Running CDC?
Clock-Domain Crossing Jul 16, 2020 Chris Giles pdf

June 2020

Better UVM Debug
UVM - Universal Verification Methodology Jun 02, 2020 tar

April 2020

ISO 26262 in Simple Terms
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
ISO 26262 Requirements Management
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
Deadlock Verification for Dummies: The Easy Way Using SVA and Formal
Formal Verification Apr 15, 2020 Mark Eslinger pdf
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft pdf

March 2020

Mind the GAP(s): Closing and Creating GAPS Between Design and Verification
Questa Design Solutions Mar 31, 2020 Chris Giles pdf
FPGA Verification Maturity: A Quantitative Analysis
FPGA Verification Mar 26, 2020 pdf
If You Don’t Know, Now You Know: Terminal Boundary Dictates Power Aware Macros
Low Power Mar 14, 2020 Progyna Khondkar pdf

January 2020

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Jan 20, 2020 Harry Foster link
Technical Paper: Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task
Functional Safety Jan 07, 2020 pdf

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

DVCon India 2026

September 1st - September 3rd

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DVCon Taiwan 2026

Tuesday, September 8, 2026

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DVCon Japan 2026

Thursday, September 10, 2026

Join Siemens EDA at DVCon Japan 2026 in Yokohama Kanagawa!