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September 2021 - Volume 17 Issue 2 (7)

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March 2022

The Best Verification Strategy You’ve Never Heard Of
Planning, Measurement and Analysis Mar 28, 2022 mp4
What Does the Sequence Say? Powering Productivity with Polymorphism
UVM - Universal Verification Methodology Mar 23, 2022 pdf
Confidently Sign-off any Low-Power Designs without Consequences
Low Power Mar 23, 2022 pdf
Path-based UPF Strategies Optimally Manage Power on your Designs
Low Power Mar 23, 2022 pdf
Formal 101 - Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 Joe Hupcey Webinar
Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 pdf
UVM Framework Release 2022.1
UVM Framework Mar 09, 2022 Bob Oden tar
Getting to Know Visualizer - Part I
Debug Mar 02, 2022 Rich Edelman Article
Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article
UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Espen Tallaksen - Emlogic Article

February 2022

Equivalence Checking for FPGA
Formal Verification Feb 25, 2022 Martin Rowe Webinar
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
Simulation Feb 02, 2022 Verification Horizons Article

January 2022

Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee pdf
Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee Webinar
Odds and Ends
Python Jan 14, 2022 Ray Salemi link

December 2021

Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal
Formal Verification Dec 20, 2021 Joe Hupcey Webinar
Logging in PYUVM
Python Dec 14, 2021 Ray Salemi link
Courtines and COCOTB Testbench Code
Python Dec 14, 2021 Ray Salemi link

November 2021

The UVM Factory
Python Nov 17, 2021 Ray Salemi link

October 2021

The Configuration Database in PYUVM
Python Oct 27, 2021 Ray Salemi link
Total Recall - What to Look for in a Memory Model Library
Simulation Oct 26, 2021 Mark Peryer Article
IC/ASIC Functional Verification Trend Report - 2020
Planning, Measurement and Analysis Oct 22, 2021 pdf
TLM 1.0 in pyuvm
Python Oct 01, 2021 Ray Salemi link

September 2021

Questa Lint - Find and Fix RTL Issues
Questa Design Solutions Sep 14, 2021 Tom Carlstedt-Duke Demo

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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