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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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Design For Test May 13, 2025 Jake Wiltgen Paper

April 2025

Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
Verification IP Apr 30, 2025 Kevin Ham pdf
Securing your FPGA Design from RTL through to the Bitstream
FPGA Verification Apr 23, 2025 Keerthi Devraj Webinar
Securing your FPGA Design from RTL through to the Bitstream
FPGA Verification Apr 23, 2025 Keerthi Devraj pdf
Faster Debug Using QuestaSim Interactive Coverage Analysis
Simulation Apr 16, 2025 Justin Royse pdf
Faster Debug Using QuestaSim Interactive Coverage Analysis
Simulation Apr 16, 2025 Justin Royse Webinar

March 2025

Faster Debug of Complex Testbenches using Visualizer
Debug Mar 05, 2025 Erik Jessen Webinar
Faster Debug of Complex Testbenches Using Visualizer
Debug Mar 05, 2025 Erik Jessen pdf

February 2025

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
FPGA Verification Feb 19, 2025 Kevin Urish pdf
Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
FPGA Verification Feb 19, 2025 Kevin Urish Webinar
IC/ASIC Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Paper
FPGA Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Paper
Introduction and Study Background
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
IC/ASIC Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster pdf
FPGA Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster pdf
Verification Effectiveness Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Verification Effort Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Design Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Language and Methodology Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Verification Technology Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Final Insights and Conclusions
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Got Coverage?
Coverage Feb 14, 2025 Rich Edelman link
DVCon 2025: A Must for Hardware Design and Verification Engineers
Standards Feb 12, 2025 Dave Rich link
Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Verification IQ Feb 12, 2025 Mark Carey pdf
Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Verification IQ Feb 12, 2025 Mark Carey Webinar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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