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September 2021 - Volume 17 Issue 2 (7)

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March 2023 - Volume 19 Issue 1 (6)

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July 2020 - Volume 16 Issue 2 (5)

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December 2019 - Volume 15 Issue 3 (3)

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January 2023

Does Your UVM Flavor Have Sprinkles?
UVM - Universal Verification Methodology Jan 20, 2023 Chris Spear link
Conclusion: Deeper Dive into Non-Trivial Bug Escapes
Planning, Measurement and Analysis Jan 15, 2023 Harry Foster link
Part 12: IC/ASIC Verification Results Trends
Planning, Measurement and Analysis Jan 09, 2023 Harry Foster link
Part 11: ASIC/IC Low Power Trends
Planning, Measurement and Analysis Jan 02, 2023 Harry Foster link
Siemens Xcelerator Academy: One Glance - All Trainings
UVM - Universal Verification Methodology Jan 01, 2023 Siemens Learning Center pdf
Learning Center: QuestaSim Training (Instructor Led)
Simulation Jan 01, 2023 Siemens Learning Center link
Learning Center: QuestaSim Training (On-Demand)
Simulation Jan 01, 2023 Siemens Learning Center link
Learning Center: Visualizer Training (On-Demand)
Debug Jan 01, 2023 Siemens Learning Center link
Learning Center: Visualizer Training (Instructor Led)
Debug Jan 01, 2023 Siemens Learning Center link
Functional Verification: Self-Paced Library
UVM - Universal Verification Methodology Jan 01, 2023 Siemens Learning Center link
SystemVerilog for Verification: Self-Paced Course
SystemVerilog Jan 01, 2023 Siemens Learning Center link
SystemVerilog UVM: Self-Paced Course
UVM - Universal Verification Methodology Jan 01, 2023 Siemens Learning Center link
Functional Verification: Badging and Certification
UVM - Universal Verification Methodology Jan 01, 2023 Siemens Learning Center link

December 2022

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 26, 2022 Harry Foster link
Part 8: IC/ASIC Resource Trends
Planning, Measurement and Analysis Dec 18, 2022 Harry Foster link
Part 9: ASIC Verification Technology Adoption Trends
Planning, Measurement and Analysis Dec 18, 2022 Harry Foster link
Harry Foster - Siemens EDA
Formal Verification Dec 08, 2022 Harry Foster mp4
Holger Busch - Infineon
Formal Verification Dec 08, 2022 Holger Busch - Infineon mp4
Katharina Ceesay-Seitz - ETH Zurich
Formal Verification Dec 08, 2022 Katharina Ceesay-Seitz mp4
Philippe Luc - Codasip
Formal Verification Dec 08, 2022 Philippe Luc - Codasip mp4
Saranyu Chattopadhyay - Stanford University
Formal Verification Dec 08, 2022 Saranyu Chattopadhyay mp4
Out of the Verification Crisis - Improving RTL Quality
Planning, Measurement and Analysis Dec 01, 2022 Harry Foster Article
Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Verification IP Dec 01, 2022 Vidushi Goel - Siemens Eda Article
Data Integrity through TLP Encryption in PCI Express®
Verification IP Dec 01, 2022 Om Prakash - Siemens Eda Article
Missing Your Buttons and Menus? Create Your Own
Debug Dec 01, 2022 Vishal Baskar Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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