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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

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March 2015 - Volume 11 Issue 1 (2)

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Show Less

December 2018

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Dec 04, 2018 Harry Foster link

November 2018

FPGA Verification Challenges and Opportunities
FPGA Verification Nov 28, 2018 Harry Foster Article
Building a Better Virtual Sequence with Portable Stimulus
Portable Stimulus Nov 28, 2018 Matthew Ballance Article
Simplifying Mixed-Signal Verification
Analog Mixed-Signal Nov 28, 2018 Article
Part 2: FPGA Verification Effectiveness Trends
Planning, Measurement and Analysis Nov 26, 2018 Harry Foster link
Part 1: FPGA Design Trends
Planning, Measurement and Analysis Nov 19, 2018 Harry Foster link
Understanding and Minimizing Study Bias (2018 Study)
Planning, Measurement and Analysis Nov 15, 2018 Harry Foster link
Prologue: The 2018 Wilson Research Group Functional Verification Study
Planning, Measurement and Analysis Nov 14, 2018 Harry Foster link

October 2018

Functional Verification Study - 2018
Planning, Measurement and Analysis Oct 15, 2018 Harry Foster Session

September 2018

UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick pdf
UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick Webinar

July 2018

Portable Stimulus versus UVM: What's the Difference?
Portable Stimulus Jul 30, 2018 John Aynsley pdf
Portable Stimulus: A New Hope
Portable Stimulus Jul 26, 2018 Tom Fitzpatrick pdf
Building An Integrated Verification Flow
Planning, Measurement and Analysis Jul 26, 2018 Neil Johnson pdf
AMS Verification Methodology for GPUs in AI and Deep Learning Applications
Analog Mixed-Signal Jul 26, 2018 pdf
Portable Stimulus from IP to SoC - Achieve More Verification
Portable Stimulus Jul 26, 2018 Matthew Ballance pdf

June 2018

Comprehensive CDC Verification with Advanced Hierarchical Data Models
Clock-Domain Crossing Jun 29, 2018 Ping Yeung Article
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Portable Stimulus Jun 29, 2018 Matthew Ballance Article
Coverage Driven Verification of NVMe Using Questa VIP (QVIP)
Verification IP Jun 29, 2018 Anurag Singh - Siemens Eda Article
Power Aware Static Verification: From Power Intent to Microarchitectural Checks of Low Power Designs - Part 2
Low Power Jun 29, 2018 Progyna Khondkar Article
Complex Addressable Registers in Mission Critical Applications
Simulation Jun 29, 2018 Ishanee Bajpai - Agnisys Article
RTL Glitch Verification
Questa Design Solutions Jun 29, 2018 Ajay Daga - Fishtail Design Automation Article
Virtual Method Upcasting & Downcasting and Their Use in UVM
UVM - Universal Verification Methodology Jun 25, 2018 Cliff Cummings pdf
Virtual Method Upcasting & Downcasting and Their Use in UVM
UVM - Universal Verification Methodology Jun 25, 2018 Cliff Cummings Conference
UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Jun 24, 2018 Tom Fitzpatrick pdf

New White Papers

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