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Show Less

January 2017

Introspection Into SystemVerilog Without Turning It Inside Out
Standards Jan 03, 2017 Dave Rich Article
Extending a Traditional VIP to Solve PHY Verification Challenges
Simulation Jan 03, 2017 Verification Methodology Team Article
Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Simulation Jan 03, 2017 Matthew Ballance Article
Boosting Simulation Performance of UVM Registers in High Performance Systems
Standards Jan 03, 2017 Verification Methodology Team Article
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
Simulation Jan 03, 2017 Dave Rich Article
Register Verification: Do We Have Reliable Specification?
Simulation Jan 03, 2017 Verification Methodology Team Article
Sequence, Sequence on the Wall – Who's the Fairest of Them All?
Standards Jan 03, 2017 Rich Edelman Article
Seven Separate Sequence Styles Speed Stimulus Scenarios
Standards Jan 03, 2017 Mark Peryer Article
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
Standards Jan 03, 2017 Mark Peryer Article
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
Standards Jan 03, 2017 Verification Methodology Team Article
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
Standards Jan 03, 2017 Mike Horn Article
Equivalence Validation of Analog Behavioral Models
Analog Mixed-Signal Jan 03, 2017 Verification Methodology Team Article
Interpreting UPF For A Mixed-Signal Design Under Test
Standards Jan 03, 2017 Verification Methodology Team Article
Using Test-IP Based Verification Techniques in a UVM Environment
Standards Jan 03, 2017 Verification Methodology Team Article
Is Your Power Aware Design Really X-Aware?
Simulation Jan 03, 2017 Verification Methodology Team Article
Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
Standards Jan 03, 2017 Verification Methodology Team Article
So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
Simulation Jan 03, 2017 Andreas Meyer Article
Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?
Verification Management Jan 03, 2017 Darron May Article
Bringing Regression Systems into the 21st Century
Verification Management Jan 03, 2017 Thom Ellis Article

December 2016

Jenkins Tutorial - Setup, Install, Configuration
Planning, Measurement and Analysis Dec 23, 2016 Darron May pdf
JUnit Plugin (required)
Planning, Measurement and Analysis Dec 23, 2016 link
Questa VRM
Planning, Measurement and Analysis Dec 23, 2016 Darron May link
Jenkins Release
Planning, Measurement and Analysis Dec 23, 2016 link
Dashboard View (optional)
Planning, Measurement and Analysis Dec 23, 2016 link
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf

DAC 2025

Exhibitor Forum: Smart Verification for Modern Complexity

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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January 2017

Introspection Into SystemVerilog Without Turning It Inside Out

Extending a Traditional VIP to Solve PHY Verification Challenges

Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Boosting Simulation Performance of UVM Registers in High Performance Systems

Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI

Register Verification: Do We Have Reliable Specification?

Sequence, Sequence on the Wall – Who's the Fairest of Them All?

Seven Separate Sequence Styles Speed Stimulus Scenarios

Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

Equivalence Validation of Analog Behavioral Models

Interpreting UPF For A Mixed-Signal Design Under Test

Using Test-IP Based Verification Techniques in a UVM Environment

Is Your Power Aware Design Really X-Aware?

Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification

So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results

Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?

Bringing Regression Systems into the 21st Century

December 2016

Jenkins Tutorial - Setup, Install, Configuration

JUnit Plugin (required)

Questa VRM

Jenkins Release

Dashboard View (optional)

Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution