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September 2021 - Volume 17 Issue 2 (7)

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June 2012 - Volume 8 Issue 2 (1)

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Show Less

June 2017

Conquering the New IP Economy
Planning, Measurement and Analysis Jun 13, 2017 Harry Foster Webinar

May 2017

SoC Verification with the Questa Flow
FPGA Verification May 17, 2017 Gordon Allan Webinar

April 2017

Hardware Emulation: Three Decades of Evolution
Simulation Apr 12, 2017 Verification Horizons Article
Sometimes the Life of a College Student and a Verification Engineer Aren’t All That Different
Simulation Apr 10, 2017 Verification Horizons Article

March 2017

Testbench Automation - Environment
UVM Framework Mar 17, 2017 Bob Oden Webinar
Testbench Automation - Introduction
UVM Framework Mar 17, 2017 Bob Oden Webinar
Testbench Automation - Testbench
UVM Framework Mar 17, 2017 Matthew Ballance Webinar
Testbench Automation - Interfaces
UVM Framework Mar 17, 2017 Bob Oden Webinar
Will Safety Critical Design Practices Improve First Silicon Success?
Functional Safety Mar 10, 2017 Harry Foster Article
UVM Tips and Tricks
Standards Mar 07, 2017 Verification Horizons Article

February 2017

Complementing Functional Verification Through the Use of Available Timing Information
Clock-Domain Crossing Feb 28, 2017 Rick Eram, Excellicon Article
Automating Tests with Portable Stimulus from IP to SoC Level
Standards Feb 28, 2017 Matthew Ballance Article

January 2017

Jenkins Installation and Setup
Planning, Measurement and Analysis Jan 10, 2017 Darron May Session
Jenkins Project Configuration
Planning, Measurement and Analysis Jan 10, 2017 Darron May Session
Jenkins VRM Integration
Planning, Measurement and Analysis Jan 10, 2017 Darron May Demo
The Fundamental Power States for UPF Modeling and Power Aware Verification
Standards Jan 04, 2017 Verification Methodology Team Article
No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model
Standards Jan 03, 2017 Rich Edelman Article
Introspection Into SystemVerilog Without Turning It Inside Out
Standards Jan 03, 2017 Dave Rich Article
Verification IP Stimulus APIs - Are They Really Easy to Use?
Simulation Jan 03, 2017 Verification Methodology Team Article
Extending a Traditional VIP to Solve PHY Verification Challenges
Simulation Jan 03, 2017 Verification Methodology Team Article
Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Simulation Jan 03, 2017 Matthew Ballance Article
Boosting Simulation Performance of UVM Registers in High Performance Systems
Standards Jan 03, 2017 Verification Methodology Team Article
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
Simulation Jan 03, 2017 Dave Rich Article
Register Verification: Do We Have Reliable Specification?
Simulation Jan 03, 2017 Verification Methodology Team Article
Sequence, Sequence on the Wall – Who's the Fairest of Them All?
Standards Jan 03, 2017 Rich Edelman Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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