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March 2014 - Volume 10 Issue 1 (4)

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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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October 2012 - Volume 8 Issue 3 (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

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March 2015 - Volume 11 Issue 1 (2)

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Data Integrity through TLP Encryption in PCI Express®
Verification IP Dec 01, 2022 Om Prakash - Siemens Eda Article
Missing Your Buttons and Menus? Create Your Own
Debug Dec 01, 2022 Vishal Baskar Article

November 2022

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Nov 28, 2022 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Nov 21, 2022 Harry Foster link
Functional Verification Study - 2022
Planning, Measurement and Analysis Nov 16, 2022 Harry Foster Session
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Nov 13, 2022 Harry Foster link
Episode 1: The Current Trends in ASIC Design and Verification
Planning, Measurement and Analysis Nov 09, 2022 Harry Foster link
Episode 2: The Current Trends in ASIC Design Verification Technology
Planning, Measurement and Analysis Nov 09, 2022 Harry Foster link
Part 4: FPGA Verification Effort Trends (Continued)
Planning, Measurement and Analysis Nov 06, 2022 Harry Foster link
Episode 2: The Current Trends in FPGA Verification
Planning, Measurement and Analysis Nov 02, 2022 Harry Foster link
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai Webinar
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai pdf

October 2022

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Oct 30, 2022 Harry Foster link
Episode 1: The Growing Complexity in Field Programmable Gate Arrays (FPGA)
Planning, Measurement and Analysis Oct 26, 2022 Harry Foster link
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma pdf
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma Webinar
Part 2: FPGA Verification Effectiveness Trends
Planning, Measurement and Analysis Oct 24, 2022 Harry Foster link
Formal and the Next Normal
Formal Verification Oct 19, 2022 Joe Hupcey Webinar
Dig a Pool of Specialized SystemVerilog Classes
SystemVerilog Oct 17, 2022 Chris Spear link
Part 1: FPGA Design Trends
Planning, Measurement and Analysis Oct 16, 2022 Harry Foster link
Prologue: The 2022 Wilson Research Group Functional Verification Study
Planning, Measurement and Analysis Oct 10, 2022 Harry Foster link

September 2022

SystemVerilog: Implicit handles
SystemVerilog Sep 06, 2022 Chris Spear link

August 2022

SystemVerilog: Class Member Visibility
SystemVerilog Aug 29, 2022 Chris Spear link

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

DVCon India 2026

September 1st - September 3rd

Join Siemens EDA at DVCon India 2026 in Bangalore!

DVCon Taiwan 2026

Tuesday, September 8, 2026

Join Siemens EDA at DVCon Taiwan 2026 in Hsinchu!

DVCon Japan 2026

Thursday, September 10, 2026

Join Siemens EDA at DVCon Japan 2026 in Yokohama Kanagawa!