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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

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Questa Design Solutions Nov 02, 2022 Vinayak Desai Webinar
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai pdf

October 2022

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Oct 30, 2022 Harry Foster link
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma pdf
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma Webinar
Formal and the Next Normal
Formal Verification Oct 19, 2022 Joe Hupcey Webinar
Dig a Pool of Specialized SystemVerilog Classes
SystemVerilog Oct 17, 2022 Chris Spear link
Part 1: The Global FPGA Semiconductor Market
Planning, Measurement and Analysis Oct 16, 2022 Harry Foster link

September 2022

SystemVerilog: Implicit handles
SystemVerilog Sep 06, 2022 Chris Spear link

August 2022

SystemVerilog: Class Member Visibility
SystemVerilog Aug 29, 2022 Chris Spear link

July 2022

The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Sumit Vishwakarma Article
Getting to Know Visualizer - Part II
Debug Jul 05, 2022 Rich Edelman Article
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article
Reflections on Users’ Experiences with SVA - Part II
SystemVerilog Jul 05, 2022 Ben Cohen Article
Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

June 2022

Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman Paper
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf
The Three Pillars of Intent-Focused Insight
Planning, Measurement and Analysis Jun 08, 2022 Harry Foster Webinar

May 2022

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar
Securing the Electronics Development Chain with IC Integrity Solutions
Formal Verification May 10, 2022 John Hallman Webinar

March 2022

The Best Verification Strategy You’ve Never Heard Of
Planning, Measurement and Analysis Mar 28, 2022 mp4
What Does the Sequence Say? Powering Productivity with Polymorphism
UVM - Universal Verification Methodology Mar 23, 2022 Rich Edelman pdf
Confidently Sign-off any Low-Power Designs without Consequences
Low Power Mar 23, 2022 pdf

FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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